Electromigration inside Logic Cells : Modeling, Analyzing and Mitigating Signal Electromigration in NanoCMOS

Posser, Gracieli/ Sapatnekar, Sachin S./ Reis, Ricardo

Springer International Publishing AG（2018/07発売）

• 製本 Paperback:紙装版/ペーパーバック版／ページ数 118 p.
• 言語 ENG
• 商品コード 9783319840413
• DDC分類 004.1

Full Description

This book describes new and effective methodologies for modeling, analyzing and mitigating cell-internal signal electromigration in nanoCMOS, with significant circuit lifetime improvements and no impact on performance, area and power. The authors are the first to analyze and propose a solution for the electromigration effects inside logic cells of a circuit. They show in this book that an interconnect inside a cell can fail reducing considerably the circuit lifetime and they demonstrate a methodology to optimize the lifetime of circuits, by placing the output, Vdd and Vss pin of the cells in the less critical regions, where the electromigration effects are reduced. Readers will be enabled to apply this methodology only for the critical cells in the circuit, avoiding impact in the circuit delay, area and performance, thus increasing the lifetime of the circuit without loss in other characteristics. 

Contents

Chapter 1. Introduction.- Chapter 2. State of the Art.- Chapter 3. Modeling Cell-internal EM.- Chapter 4. Current Calculation.- Chapter 5. Experimental Setup.- Chapter 6.Results.- Chapter 7. Analyzing the Electromigration Effects on Different Metal Layers.- Chapter 8. Conclusions.