Full Description
This is the first book that sums up test-related modeling of digital circuits and systems by a new structural-decision-diagrams model. The model represents structural and functional information jointly and opens a new area of research.
The book introduces and discusses applications of two types of structural decision diagrams (DDs): low-level, structurally synthesized binary DDs (SSBDDs) and high-level DDs (HLDDs) that enable diagnostic modeling of complex digital circuits and systems.
Topics and features:
Provides the definition, properties and techniques for synthesis, compression and optimization of SSBDDs and HLDDs
Provides numerous working examples that illustrate the key points of the text
Describes applications of SSBDDs and HLDDs for various electronic design automation (EDA) tasks, such as logic-level fault modeling and simulation, multi-valued simulation, timing-critical path identification, and test generation
Discusses the advantages of the proposed model to traditional binary decision diagrams and other traditional design representations
Combines SSBDDs with HLDDs for multi-level representation of digital systems for enabling hierarchical and cross-level solving of complex test-related tasks
This unique book is aimed at researchers working in the fields of computer science and computer engineering, focusing on test, diagnosis and dependability of digital systems. It can also serve as a reference for graduate- and advanced undergraduate-level computer engineering and electronics courses.
Three authors are affiliated with the Dept. of Computer Systems at the Tallinn University of Technology, Estonia: Raimund Ubar is a retired Professor, Jaan Raik and Maksim Jenihhin are tenured Professors. Artur Jutman, PhD, is a researcher at the same university and the CEO of Testonica Lab Ltd., Estonia.
Contents
Chapter 1: Introduction.- Chapter 2: Overview of structural decision diagrams.- Chapter 3: Structurally Synthesized Binary Decision Diagrams.- Chapter 4: Fault modeling in digital circuits.- Chapter 5: Logic-level fault simulation.- Chapter 6: Test generation, fault diagnosis and testability.- Chapter 7: High-Level Decision Diagrams.- Chapter 8: Test generation for microprocessors with HLDDs.
