VLSI Physical Design: from Graph Partitioning to Timing Closure （2011）

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VLSI Physical Design: from Graph Partitioning to Timing Closure （2011）

Kahng, Andrew B./ Lienig, Jens/ Markov, Igor L.

ウェブストア価格 ¥19,511（本体¥17,738）
Springer（2014/10発売）
外貨定価 US$ 89.99
ポイント 177pt

オンデマンド(OD/POD)版です。キャンセルは承れません。

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製本 Paperback:紙装版/ペーパーバック版／ページ数 310 p.
言語 ENG
商品コード 9789400790209
DDC分類 621

Full Description

Design and optimization of integrated circuits are essential to the creation of new semiconductor chips, and physical optimizations are becoming more prominent as a result of semiconductor scaling. Modern chip design has become so complex that it is largely performed by specialized software, which is frequently updated to address advances in semiconductor technologies and increased problem complexities. A user of such software needs a high-level understanding of the underlying mathematical models and algorithms. On the other hand, a developer of such software must have a keen understanding of computer science aspects, including algorithmic performance bottlenecks and how various algorithms operate and interact.

"VLSI Physical Design: From Graph Partitioning to Timing Closure"

introduces and compares algorithms that are used during the physical design phase of integrated-circuit design, wherein a geometric chip layout is produced starting from an abstract circuit design. The emphasis is on essential and fundamental techniques, ranging from hypergraph partitioning and circuit placement to timing closure.

1 Introduction. 2 Netlist and System Partitioning. 3 Chip Planning. 4 Global and Detailed Placement. 5 Global Routing. 6 Detailed Routing. 7 Specialized Routing. 8 Timing Closure. A Solutions to Chapter Exercises. B Example CMOS Cell Layouts.