Description
This new volume introduces various VLSI (very-large-scale integration) architecture for DSP filters, speech filters, and image filters, detailing their key applications and discussing different aspects and technologies used in VLSI design, models and architectures, and more. The volume explores the major challenges with the aim to develop real-time hardware architecture designs that are compact and accurate. It provides useful research in the field of computer arithmetic and can be applied for various arithmetic circuits, for their digital implementation schemes, and for performance considerations.
Table of Contents
1. Evolution of 1-D, 2-D, and 3-D Lifting Discrete Wavelet Transform VLSI Architecture
C. S. N. Koushik, Abhishek Choubey, Shruti Bhargava Choubey, and D. Naresh
2. Execution of Lifting-Scheme Discrete Wavelet Transform by Canonical Signed Digit Multiplier
Gundugonti Kishore Kumar and Narayanam Balaji
3. Radix-8 Booth Multiplier in Terms of Power and Area Efficient for Application in the Field of 2D DWT Architecture
Gundugonti Kishore Kumar and Narayanam Balaji
4. Design and Performance Evaluation of Energy Efficient 8-Bit ALU at Ultra-Low Supply Voltages Using FinFET with 20nm Technology
Vallabhuni Vijay, Pittala Chandra Shekar, Shaik Sadulla, Putta Manoja, Rallabhandy Abhinaya, Merugu Rachana, and Nakka Nikhil
5. Design and Statistical Analysis of Strong Arbiter PUFs for Device Authentication and Identification
Kurra Anil Kumar and Usha Rani Nelakuditi
6. An Impact of Aging on Arbiter Physical Unclonable Functions
Kurra Anil Kumar and Usha Rani Nelakuditi
7. Advanced Power Management Methodology for SoCs Using UPF
Usha Rani Nelakuditi, Naveen Kumar Challa, and Kurra Anil Kumar
8. Architecture Design: Network-on-Chip
N. Ashok Kumar, A. Kavitha, P. Venkatramana, and Durgesh Nandan
9. Routing Strategy: Network-on-Chip Architectures
N. Ashok Kumar, S. Vishnu Priyan, P. Venkatramana, and Durgesh Nandan
10. Self-Driven Clock Gating Technique for Dynamic Power Reduction of High-Speed Complex Systems
Roopa R. Kulkarni and S. Y. Kulkarni
11. Optimization of SoC Sub-Circuits Using Mathematical Modeling
Magnanil Goswami
12. An Efficient Design of D Flip Flop in Quantum-Dot Cellular Automata (QCA) for Sequential Circuits
Birinderjit Singh Kalyan, Harpreet Kaur, Khushboo Pachori, and Balwinder Singh
13. Design and Performance Analysis of Digitally Controlled DC-DC Converter
Subhransu Padhee, Madhusmita Mohanty, and Ambarish Panda
