Electromigration Modeling at Circuit Layout Level

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Electromigration Modeling at Circuit Layout Level

  • 著者名:Tan, Cher Ming/He, Feifei
  • 価格 ¥10,117 (本体¥9,198)
  • Springer(2013/03/16発売)
  • 春分の日の三連休!Kinoppy 電子書籍・電子洋書 全点ポイント30倍キャンペーン(~3/22)
  • ポイント 2,730pt (実際に付与されるポイントはご注文内容確認画面でご確認下さい)
  • 言語:ENG
  • ISBN:9789814451208
  • eISBN:9789814451215

ファイル: /

Description

Integrated circuit (IC) reliability is of increasing concern in present-day IC technology where the interconnect failures significantly increases the failure rate for ICs with decreasing interconnect dimension and increasing number of interconnect levels. Electromigration (EM) of interconnects has now become the dominant failure mechanism that determines the circuit reliability. This brief addresses the readers to the necessity of 3D real circuit modelling in order to evaluate the EM of interconnect system in ICs, and how they can create such models for their own applications. A 3-dimensional (3D) electro-thermo-structural model as opposed to the conventional current density based 2-dimensional (2D) models is presented at circuit-layout level.

Table of Contents

Introduction.- 3D Circuit Model Construction and Simulation.- Comparison of EM Performance in Circuit Structure and Test Structure.- Interconnect EM Reliability Modeling at Circuit Layout Level.- Conclusion.

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