Interconnection Networks

個数:1
紙書籍版価格
¥23,058
  • 電子書籍
  • ポイントキャンペーン

Interconnection Networks

  • 著者名:Duato, Jose/Yalamanchili, Sudhakar/Ni, Lionel
  • 価格 ¥16,365 (本体¥14,878)
  • Morgan Kaufmann(2002/08/06発売)
  • 春分の日の三連休!Kinoppy 電子書籍・電子洋書 全点ポイント30倍キャンペーン(~3/22)
  • ポイント 4,440pt (実際に付与されるポイントはご注文内容確認画面でご確認下さい)
  • 言語:ENG
  • ISBN:9781558608528
  • eISBN:9780080508993
  • NDC分類:548.48

ファイル: /

Description

The performance of most digital systems today is limited by their communication or interconnection, not by their logic or memory. As designers strive to make more efficient use of scarce interconnection bandwidth, interconnection networks are emerging as a nearly universal solution to the system-level communication problems for modern digital systems. Interconnection networks have become pervasive in their traditional application as processor-memory and processor-processor interconnect. Point-to-point interconnection networks have replaced buses in an ever widening range of applications that include on-chip interconnect, switches and routers, and I/O systems. In this book, the authors present in a structured way the basic underlying concepts of most interconnection networks and provide representative solutions that have been implemented in the industry or proposed in the research literature.* Gives a coherent, comprehensive treatment of the entire field* Presents a formal statement of the basic concepts, alternative design choices, and design trade-offs* Provides thorough classifications, clear descriptions, accurate definitions, and unified views to structure the knowledge on interconnection networks* Focuses on issues critical to designers

Table of Contents

ForewordForeword to the First PrintingPrefaceChapter 1 - IntroductionChapter 2 - Message Switching LayerChapter 3 - Deadlock, Livelock, and StarvationChapter 4 - Routing AlgorithmsChapter 5 - CollectiveCommunicationSupportChapter 6 - Fault-Tolerant RoutingChapter 7 - Network ArchitecturesChapter 8 - Messaging Layer SoftwareChapter 9 - Performance EvaluationAppendix A - Formal Definitions for Deadlock AvoidanceAppendix B - AcronymsReferencesIndex

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