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Full Description
We are about to enter a period of radical change in computer architecture. It is made necessary by adL)anCeS in processing tech- nology that will make it possible to build devices exceeding in performance and complexity anything conceived in the past. These advances the logical extension of large - to very-large-scale in- J tegration (VLSI) are all but inevitable. With the large number of shlitching elements available in a sinqle chip as promised by VLSI technology, the question that arises naturally is: What can hle do hlith this technology and hOhl can hle best utilize it? The final anShler, hlhatever it may be, hlill be based on architectu- ral concepts that probably hlill depart, in several cases, from past and present practices. Furthermore, as hle continue to build increasingly pOhlerful microprocessors permitted by VLSI process advances, the method of efficiently interconnecting them hlill become more and more important. In fact one serious drahlback of VLSI technology is the limited number of pins on each chip. While VLSI chips provide an exponentially grOhling number of gates, the number of pins they provide remains almost constant.
As a result communication becomes a very difficult design problem in the interconnection of VLSI chips. Due to the insufficient commu- nication pOhler and the high design cost of VLSI chips, computer systems employing VLSI technology hlill thus need to employ many architectural concepts that depart sharply from past and present practices.
Contents
I: VLSI Architectures for Microprocessors.- 1. Micro/370.- 2. Microarchitecture of the HP9000 Series 500 CPU.- 3. The Dragon Computer System: An Early Overview.- 4. The VLSI VAX Chip Set Microarchitecture.- 5. External and Internal Architecture of the P32, a 32 Bit Microprocessor.- 6. A Highly Regular Peripheral Processor.- II: VLSI Architectures for Image Processing.- 7. Scape: A VLSI Chip Architecture for Image Processing.- 8. VLSI Architectures for Computer Graphics.- III: VLSI Architectures for Systolic Arrays.- 9. Experience with the CMU Programmable Systolic Chip.- IV: Testing of VLSI Chips.- 10. Microarchitecture of the MC 68000 and Evaluation of a Self Checking Version.
