Synthesizable VHDL Design for FPGAs

Bezerra, Eduardo Augusto/ Lettnin, Djones Vinicius

Springer International Publishing AG（2016/08発売）

• 製本 Paperback:紙装版/ペーパーバック版／ページ数 157 p.
• 言語 ENG
• 商品コード 9783319377339
• DDC分類 005.1

Full Description

The methodology described in this book is the result of many years of research experience in the field of synthesizable VHDL design targeting FPGA based platforms. Usually VHDL books describe both, synthesis and simulation aspects of the language, but in this book the reader is conducted just through the features acceptable by synthesis tools.