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Full Description
This book addresses the technological contributions and developments of advanced hardware for Machine Learning (ML) computing systems. The authors discuss state-of-the-art progress in this area (and related topics) as well as reporting on their application to diverse fields. This is achieved by chapters covering the entire spectrum of research activities to include design and applications, with a focus on high performance and dependable operation. The entire hardware stack (from circuit, to architecture, up to the system level) is discussed in detail. The book will cover innovative material as well as tutorials, reviews and surveys of current theoretical/experimental results, design methodologies and applications over a wide spectrum of scope for an enlarged readership, so to include engineers as well as scientists.
Contents
High performance machine learning accelerators on fpga.- Floating point arithmetic in deep neural networks evaluation and implementation of conventional and emerging formats with mixed precision strategies.- High performance computing architectures for ml.- High performance domain specific computing architectures for machine learning.- Edge ai training accelerator design.- Accelerating machine learning with unconventional architectures.- Mram based energy efficient computing architectures for accelerators machine learning.- Energy efficient data aware computation in computing in memory architecture.- Stochastic computing applied to morphological neural networks.- Approximate multipliers for machine learning applications.- Edge computing meets giant ai innovations in large language model efficiency.- Chiplet based accelerator design for scalable training of transformer based generative adversarial networks.- Energy consumption in generative ai insights from large language models inference.- Sustainable and responsible generative artificial intelligence gen ai a survey.- Low power machine learning realization techniques on biomedical wearable devices.- Application of algorithm and hardware co design in the hardware accelerator of visual slam frontend.- Application of algorithm and hardware co design in the hardware accelerator of visual slam backend.- Hardware efficient designs for spiking neural networks.
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