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Description
This book provides a comprehensive introduction the reliability, and electronic materials innovations in advanced memory device packaging from component to system level. Special features of this book are sections covering not only the advanced packaging materials, but also system level packaging and integration in memory modules and solid state drives (SSD).
The book is an extremely useful and applicable guide to professionals and students on materials reliability in memory device packaging - from component to system level.
Influences of Electronic Materials Properties on Packaging Reliability.- Mechanical and Thermal Stress of Encapsulant and New Materials in Memory Packaging.- Materials Development for Future Data Center Applications.- Advanced Chiplets and Heterogenous Integration in Memory Device Packaging.- Hybrid Bonding Device Packaging.- Hardware Reliability for Memory Modules and SSDs.- Innovative Sustainable Electronics Materials in Advanced Memory Packaging.- PCB and Substrate in Future Memory Applications.
Dr. Chong Leong, Gan received the B.S. degree in Chemical Engineering from National University of Malaysia in 2000, M.S. degree in Chemical Instrumentation in 2003 from University Science Malaysia, and Ph.D. in Nanoelectronic Engineering from University Malaysia Perlis, Malaysia in 2015. He is SMIEEE, Fellow of Institute of Materials Malaysia, Fellow of Malaysian Institute of Chemistry, Fellow of Institute of Physics ,UK and Royal Society of Chemistry, UK. Since 2000, he has been a Quality and Reliability MTS with Intel FPGA, Product Engineering Manager with Osram Opto-Semiconductors, Senior R&D Engineering Manager with Western Digital and currently working as Package Characterization Director with Micron Technology Inc. He is recipient of IEEE EPS Distinguish Technical Leadership award in 2021, Emerald Outstanding Reviewer in 2021 ASME JEP Reviewer of the Year in 2022. His research interests including semiconductor packaging reliability, material characterization, nanomaterials, and radiation reliability. He has published more than 70 international journal articles, 1 book with Springer Publisher. CL serves as Editorial boards with more than 30 international journals and with 22 patents issued/ filing in US and China patent offices.
Chen-Yu, Huang received his Ph.D. in the Institute of Mechanical Engineering from Chang Gung University, Taiwan 2012. He has over 10 years of R&D experience in advanced packaging and wafer form assembly process integration. He was the 2.5D and Fan-out assembly project manager in SPIL Corporate R&D center (merged with ASE) from 2012 to 2019. After that, he moved to the Micron Memory Taiwan Co., Ltd. to be a technology development and process integration engineer and focus on hybrid 3D stacking DRAM and HBM (High Band Memory) products. He has authored 1 book with Springer Publishing, more than 30 Journal and conference publications covering warpage, stresses, reliability, failure analysis, material characterization relative topics in electronic packaging investigation.
