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Full Description
This book covers analysis and design of PLL-based frequency modulators, used in the hearth of modern FMCW radars. The desired radar performance targets are translated into the modulator specifications first. The authors then focus on describing the optimal modulator architecture, with special care given to core building blocks of the system. The central analog building block described is a novel charge integrating-based chirp generator, which breaks limits of similar art in the field where performance (noise, area) is typically traded for power. The book then continues to describe power-efficient, mixed-signal background calibration engine implementation, which when applied in context of the presented system, ensures pristine linearity of the generated chirps. The detailed design guide shows how robust duty-cycling can be enabled, to ensure low-power consumption of the system, without compromise in radar performance. A complete overview of all circuit-level building blocks is provided, to ensure that readers can tackle every aspect of the system. Finally, the book covers description of a rigorous chirp-linearity and phase-noise performance characterization methodology, critical for evaluation of radar system performance metrics.
This book provides insightful design guidelines for DTC-based fractional-N PLL synthesizers and QDAC-based FMCW frequency modulators for both academic researchers and industry IC design engineers.
Contents
Introduction.- A 10GHz Sub Sampling PLL Chirp Synthesizer using a Charge.- Integrating Digital-to-Analog Converter (DAC).- A 16 GHz Duty-Cycled Charge Pump PLL-based Chirp Synthesizer.- Conclusion.
