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Full Description
This book demonstrates the breadth and depth of IP protection through logic locking, considering both attacker/adversary and defender/designer perspectives. The authors draw a semi-chronological picture of the evolution of logic locking during the last decade, gathering and describing all the DO's and DON'Ts in this approach. They describe simple-to-follow scenarios and guide readers to navigate/identify threat models and design/evaluation flow for further studies. Readers will gain a comprehensive understanding of all fundamentals of logic locking.
Contents
Basics of VLSI Design.- Basics of VLSI Testing and Debug.- IP Protection in VLSI Design: A Historical View.- Making a Case for Logic Locking.- Fundamentals of Logic Locking.- Infrastructure around Logic Locking.- Impact of Satisfiability Solvers on Logic Locking.- Post-Satisfiability Era: Countermeasures and Threats.- Design-for-Testability and its Impact on Logic Locking.- Emergence of Cutting-edge Technologies on Logic Locking.- Logic Locking in Future IC Supply Chain Environments.- Multilayer Approach to Logic Locking.- A Step-by-Step Guide for Protecting/Locking Your IP.- A Step-by-Step Guide for Security Evaluation of Protected/Locked IP.
