On-Chip Training NPU - Algorithm, Architecture and SoC Design

Han, Donghyeon/ Yoo, Hoi-Jun

Springer International Publishing AG（2023/07発売）

• 製本 Hardcover:ハードカバー版／ページ数 237 p.
• 商品コード 9783031342363

Full Description

Unlike most available sources that focus on deep neural network (DNN) inference, this book provides readers with a single-source reference on the needs, requirements, and challenges involved with on-device, DNN training semiconductor and SoC design. The authors include coverage of the trends and history surrounding the development of on-device DNN training, as well as on-device training semiconductors and SoC design examples to facilitate understanding.

Contents

Chapter 1 Introduction.- Chapter 2 A Theoretical Study on Artificial Intelligence Training.- Chapter 3 New Algorithm 1: Binary Direct Feedback Alignment for Fully-Connected layer.- Chapter 4 New Algorithm 2: Extension of Direct Feedback Alignment to Convolutional Recurrent Neural Network.- Chapter 5 DF-LNPU: A Pipelined Direct Feedback Alignment based Deep Neural Network Learning Processor for Fast Online Learning.- Chapter 6 HNPU-V1: An Adaptive DNN Training Processor Utilizing Stochastic Dynamic Fixed-point and Active Bit-precision Searching.- Chapter 7 HNPU-V2: An Energy-efficient DNN Training Processor for Robust Object Detection with Real-World Environmental Adaptation.- Chapter 8 An Overview of Energy-efficient DNN Training Processors.- Chapter 9 Conclusion.