Phase-Locked Frequency Generation and Clocking : Architectures and circuits for modern wireless and wireline systems (Materials, Circuits and Devices)

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Phase-Locked Frequency Generation and Clocking : Architectures and circuits for modern wireless and wireline systems (Materials, Circuits and Devices)

Rhee, Woogeun (EDT)

ウェブストア価格 ¥33,928（本体¥30,844）
Institution of Engineering and Technology（2020/06発売）
外貨定価 US$ 180.00
読書週間ポイント2倍キャンペーン対象商品（～11/9）
ポイント 616pt

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製本 Hardcover:ハードカバー版／ページ数 736 p.
言語 ENG
商品コード 9781785618857
DDC分類 621.3815

Full Description

Phase-Locked Frequency Generation and Clocking covers essential topics and issues in current Phase-Locked Loop design, from a light touch of fundamentals to practical design aspects. Both wireless and wireline systems are considered in the design of low noise frequency generation and clocking systems. Topics covered include architecture and design, digital-intensive Phase-Locked Loops, low noise frequency generation and modulation, clock-and-data recovery, and advanced clocking and clock generation systems.

The book not only discusses fundamental architectures, system design considerations, and key building blocks but also covers advanced design techniques and architectures in frequency generation and clocking systems. Readers can expect to gain insights into phase-locked clocking as well as system perspectives and circuit design aspects in modern Phase-Locked Loop design.

Part I: Basic architectures and system perspectives

Chapter 1: Evolution of monolithic phase-locked loops
Chapter 2: Fractional-N frequency synthesis
Chapter 3: Clock data recovery: a system perspective
Chapter 4: Silicon-based THz frequency synthesizers with wide locking range

Part II: Digital-intensive phase-locked loops

Chapter 5: Time-to-digital converters
Chapter 6: Bang-bang digital PLLs for wireless systems
Chapter 7: Hybrid PLLs
Chapter 8: Spur mitigation techniques for DPLL architecture
Chapter 9: Fully synthesized digital PLL
Chapter 10: Ultra-low-power ADPLL

Part III: Low-noise frequency generation and modulation

Chapter 11: Integrated LC oscillators
Chapter 12: Mm-wave and sub-THz CMOS VCOs
Chapter 13: Ultra-low phase noise ADPLL for millimeter wave
Chapter 14: DTC-based subsampling PLLs for low-noise synthesis and two-point modulation
Chapter 15: Hybrid two-point modulation with 1b high-pass modulation and embedded FIR filtering

Part IV: Clock-and-data recovery and clocking

Chapter 16: An overview of CDR in ultra-high-speed wireline transceivers
Chapter 17: Clock and data recovery for optical links
Chapter 18: Digital clock and data recovery circuits
Chapter 19: Spread spectrum clock generator: a low-cost EMI solution
Chapter 20: High-performance CMOS clock distribution

Part V: Advanced clock/frequency generation

Chapter 21: Sub-sampling PLL techniques
Chapter 22: PLLs with nested frequency-locked loop
Chapter 23: Time amplified charge pump PLL
Chapter 24: Multiplying DLLs
Chapter 25: Wideband PLLs