Low Power Design with High-Level Power Estimation and Power-Aware Synthesis （2012）

Ahuja, Sumit/ Lakshminarayana, Avinash/ Shukla, Sandeep Kumar

Springer-Verlag New York Inc.（2014/10発売）

• 製本 Paperback:紙装版/ペーパーバック版／ページ数 170 p.
• 言語 ENG
• 商品コード 9781489987808
• DDC分類 621

Full Description

This book presents novel research techniques, algorithms, methodologies and experimental results for high level power estimation and power aware high-level synthesis. Readers will learn to apply such techniques to enable design flows resulting in shorter time to market and successful low power ASIC/FPGA design.

Contents

Introduction.- Related Work.- Background.- Architectural Selection using High Level Synthesis.- Statistical Regression Based Power Models.- Coprocessor Design Space Exploration Using High Level Synthesis.- Regression-based Dynamic Power Estimation for FPGAs.- High Level Simulation Directed RTL Power Estimation.- Applying Verification Collaterals for Accurate Power Estimation.- Power Reduction using High-Level Clock-gating.- Model-Checking to exploit Sequential Clock-gating.- System Level Simulation Guided Approach for Clock-gating.- Conclusions.