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Full Description
Since their introduction in 1984, Field-Programmable Gate Arrays (FPGAs) have become one of the most popular implementation media for digital circuits and have grown into a $2 billion per year industry. As process geometries have shrunk into the deep-submicron region, the logic capacity of FPGAs has greatly increased, making FPGAs a viable implementation alternative for larger and larger designs. To make the best use of these new deep-submicron processes, one must re-design one's FPGAs and Computer- Aided Design (CAD) tools.
Architecture and CAD for Deep-Submicron FPGAs addresses several key issues in the design of high-performance FPGA architectures and CAD tools, with particular emphasis on issues that are important for FPGAs implemented in deep-submicron processes.
Three factors combine to determine the performance of an FPGA: the quality of the CAD tools used to map circuits into the FPGA, the quality of the FPGA architecture, and the electrical (i.e. transistor-level) design of the FPGA. Architecture and CAD for Deep-Submicron FPGAs examines all three of these issues in concert.
In order to investigate the quality of different FPGA architectures, one needs CAD tools capable of automatically implementing circuits in each FPGA architecture of interest. Once a circuit has been implemented in an FPGA architecture, one next needs accurate area and delay models to evaluate the quality (speed achieved, area required) of the circuit implementation in the FPGA architecture under test. This book therefore has three major foci: the development of a high-quality and highly flexible CAD infrastructure, the creation of accurate area and delay models for FPGAs, and the study of several important FPGA architectural issues.
Architecture and CAD for Deep-Submicron FPGAs is an essential reference for researchers, professionals and students interested in FPGAs.
Contents
1 Introduction.- 1.1 Overview of FPGAs.- 1.2 FPGA Architectural Issues.- 1.3 Approach and CAD Tools.- 1.4 Book Organization.- 1.5 Acknowledgments.- 2 Background and Previous Work.- 2.1 FPGA Architecture.- 2.2 CAD for FPGAs.- 2.3 Summary.- 3 CAD Tools: Packing and Placement.- 3.1 Logic Block Packing.- 3.2 Placement: VPR.- 3.3 Summary.- 4 Routing Tools and Routing Architecture Generation.- 4.1 Position within the CAD flow.- 4.2 Architecture Parameterization and Generation.- 4.3 Routability-Driven Router.- 4.4 Timing-Driven Router.- 4.5 Delay Extraction and Timing Analysis.- 4.6 Router and Placement Algorithm Validation.- 4.7 Summary.- 5 Global Routing Architecture.- 5.1 Motivation.- 5.2 Experimental Methodology.- 5.3 Experimental Results: Directionally-Biased Routing.- 5.4 Experimental Results: Non-Uniform Routing.- 5.5 Summary.- 6 Cluster-Based Logic Blocks.- 6.1 Motivation.- 6.2 Experimental Methodology.- 6.3 Cluster Inputs Required vs. Cluster Size.- 6.4 Flexibility of Logic Block to Routing Interconnect vs. Cluster Size.- 6.5 Speed and Area-Efficiency vs. Cluster Size.- 6.5.1 Discussion of Delay vs. Cluster Size Results.- 6.6 Effect of Cluster Size on Compile Time.- 6.7 Summary.- 7 Detailed Routing Architecture.- 7.1 Motivation.- 7.2 Experimental Methodology.- 7.3 Single Wire Length Architectures.- 7.4 Two Types of Wire Segment Architectures.- 7.5 Internal Population.- 7.6 Wire Spacing for Speed.- 7.7 Overall Architecture Comparison.- 7.8 Summary.- 8 Conclusions and Future Work.- 8.1 Summary and Contributions.- 8.2 Future Work.- B.1 Transistor-Level Schematics and Assumptions.- B.1.1 FPGA Routing Structures.- Gate Boosting.- Buffers.- Connection Block to Logic Block Input Pins.- B.1.2 Logic Block Structures.- B.2 Delay and RC-Equivalent Circuit Extraction.- C.1 SizingPass Transistor Routing Switches.- C.2 Sizing Tri-State Buffer Routing Switches.- C.3 Tri-State Buffers in Output Pin Connection Blocks.- C.4 Metal Width and Spacing.- References.
