Low Power Networks-on-Chip

Silvano, Cristina (EDT)/ Lajolo, Marcello (EDT)/ Palermo, Gianluca (ED

Springer Verlag（2010/10発売）

• 製本 Hardcover:ハードカバー版／ページ数 287 p.
• 言語 ENG
• 商品コード 9781441969101
• DDC分類 621.381531

Full Description

In recent years, both Networks-on-Chip, as an architectural solution for high-speed interconnect, and power consumption, as a key design constraint, have continued to gain interest in the design and research communities. This book offers a single-source reference to some of the most important design techniques proposed in the context of low-power design for networks-on-chip architectures.

Contents

Network-on-Chip Power Estimation.- Timing.- synchronous/asynchronous communication.- Network-on-Chip link design.- Topology exploration.- Network-on-Chip support for CMP/MPSoCs.- Network design for 3D stacked logic and memory.- Beyond the wired Network-on-Chip.