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Full Description
The DSM era of semiconductors has brought about new and stringent requirements for the creation of physical design verification and mask preparation control file runsets. With the rapid adoption of the fabled semiconductor model, and the association rise in these foundry supplied "downloadable" tool support files, a great deal of expertise on how to create and modify has been lost. This book reviews the fundamental concepts behind structures runset creation, modification, and debug for modern DSM processes. This book will address the area of control file creation for physical design verification and mask preparation. These files have increased in complexity and functionality at a pace similar to the increase in complexity of the chip design on new advanced processes. The book will also cover debug, modification, and migration methodologies for existing and foundry supplied runsets.
Contents
Introduction.- What is physical design verification?.- Design rule checking concepts.- Layout versus schematic concepts.- Design application checking concepts.- RC Parasitic extraction concepts.- Mask data preparation concepts.- Reticle enhancement technology concepts.- Modular runset methodologies.- Checking methodologies.- Runset optimizations.
