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基本説明
Features - Architecting assertion suites with System Verilog Assertions; Consistency issues in formal specifications.
Full Description
Integrating formal property verification (FPV) into an existing design process raises several interesting questions. Have I written enough properties? Have I written a consistent set of properties? What should I do when the FPV tool runs into capacity issues? This book develops the answers to these questions and fits them into a roadmap for formal property verification - a roadmap that shows how to glue FPV technology into the traditional validation flow. A Roadmap for Formal Property Verification explores the key issues in this powerful technology through simple examples - you do not need any background on formal methods to read most parts of this book.
Contents
Languages for Temporal Properties.- How Does the Property Checker Work?.- Is My Specification Consistent?.- Have I Written Enough Properties?.- Design Intent Coverage.- Test Generation Games.- A Roadmap for Formal Property Verification.
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