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Full Description
The text discusses the designing of field-programmable gate array-based green computing circuits for efficient green communication. It will help senior undergraduate, graduate students, and academic researchers from diverse engineering domains such as electrical, electronics and communication, and computer.
Discusses hardware description language coding of green communication computing (GCC) circuits
Presents field-programmable gate arrays-based power-efficient models
Explores the integrations of universal asynchronous receiver/transmitter and field-programmable gate arrays
Covers architecture and programming tools of field-programmable gate arrays
Showcases Verilog and VHDL codes for green computing circuits such as finite impulse response filter, parity checker, and packet counter
The text discusses the designing of energy-efficient network components, using low voltage complementary metal-oxide semiconductors, high-speed transceiver logic, and stub series-terminated logic input/output standards. It showcases how to write Verilog and VHDL codes for green computing circuits including finite impulse response filter, packet counter, and universal asynchronous receiver-transmitter.
Contents
Chapter 1
Introduction to Green Communication Computing (GCC)
Chapter 2
Field Programmable Gate Arrays (FPGA)
Chapter 3
HDL Coding of GCC Circuits
Chapter 4
LVCMOS based UART for GCC
Chapter 5
SSTL based UART of GCC
Chapter 6
HSTL based UART for GCC
Chapter 7
MOBILE DDR based UART for GCC
Chapter 8
LVCMOS based FIR Filter for GCC
Chapter 9
SSTL based FIR Filter of GCC
Chapter 10
HSTL based FIR Filter for GCC
Chapter 11
MOBILE DDR based FIR Filter for GCC
Chapter 12
LVCMOS based Packet Counter for GCC
Chapter 13
SSTL based Packet Counter of GCC
Chapter 14
HSTL based Packet Counter for GCC
Chapter 15
MOBILE DDR based Packet Counter for GCC
