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基本説明
Addresses "front end" questions and issues encountered in using the Verilog HDL, during all the stages of Hardware Design, Synthesis and Verification. The latest Verilog-2001 and System-Verilog have also been referred to in this book.
Full Description
Over the 20 year history of Verilog, every Verilog engineer has developed his own personal "bag of tricks" for coding with Verilog. The book presents dozens of Verilog tricks of the trade on how to best use the Verilog HDL for modeling designs at various level of abstraction, and for writing test benches to verify designs.
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