A Parallel Algorithm Synthesis Procedure for High-Performance Computer Architectures (Series in Computer Science (Kluwer Academic/plenum Publishers).)

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A Parallel Algorithm Synthesis Procedure for High-Performance Computer Architectures (Series in Computer Science (Kluwer Academic/plenum Publishers).)

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  • 製本 Hardcover:ハードカバー版/ページ数 108 p.
  • 言語 ENG
  • 商品コード 9780306477430
  • DDC分類 005.275

Full Description


Despite five decades of research, parallel computing remains an exotic, frontier technology on the fringes of mainstream computing. Its much-heralded triumph over sequential computing has yet to materialize. This is in spite of the fact that the processing needs of many signal processing applications continue to eclipse the capabilities of sequential computing. The culprit is largely the software development environment. Fundamental shortcomings in the development environment of many parallel computer architectures thwart the adoption of parallel computing. Foremost, parallel computing has no unifying model to accurately predict the execution time of algorithms on parallel architectures. Cost and scarce programming resources prohibit deploying multiple algorithms and partitioning strategies in an attempt to find the fastest solution. As a consequence, algorithm design is largely an intuitive art form dominated by practitioners who specialize in a particular computer architecture. This, coupled with the fact that parallel computer architectures rarely last more than a couple of years, makes for a complex and challenging design environment.To navigate this environment, algorithm designers need a road map, a detailed procedure they can use to efficiently develop high performance, portable parallel algorithms. The focus of this book is to draw such a road map. The Parallel Algorithm Synthesis Procedure can be used to design reusable building blocks of adaptable, scalable software modules from which high performance signal processing applications can be constructed. The hallmark of the procedure is a semi-systematic process for introducing parameters to control the partitioning and scheduling of computation and communication. This facilitates the tailoring of software modules to exploit different configurations of multiple processors, multiple floating-point units, and hierarchical memories. To showcase the efficacy of this procedure, the book presents three case studies requiring various degrees of optimization for parallel execution.

Table of Contents

List of Figures                                    vii
List of Tables ix
Acknowledgments xi
1. INTRODUCTION 1 (4)
1 Notation and Conventions 2 (1)
2 Chapter Organization 3 (2)
2. PARALLEL COMPUTING 5 (8)
1 Architectures 6 (3)
2 Programming Models 9 (1)
3 Performance Metrics 10 (3)
3. PARALLEL ALGORITHM SYNTHESIS PROCEDURE 13 (16)
1 Architectural Model for Algorithm Synthesis 14 (1)
2 Synthesis Procedure 15 (10)
3 Related Work 25 (4)
4. REVIEW OF MATRIX FACTORIZATION 29 (12)
1 Givens-based Solution Procedures 31 (5)
2 Householder-based Solution Procedures 36 (5)
5. CASE STUDY 1: PARALLEL FAST GIVENS QR 41 (34)
1 Parallel Fast Givens Algorithm 42 (9)
2 Communication Procedures 51 (8)
3 Related Work 59 (1)
4 Experimental Results 60 (15)
6. CASE STUDY 2: PARALLEL COMPACT WY QR 75 (14)
1 Parallel Compact WY Algorithm 77 (6)
2 Related Work 83 (1)
3 Experimental Results 83 (6)
7. CASE STUDY 3: PARALLEL BIDIAGONALIZATION 89 (12)
1 Parallel Matrix Bidiagonalization Algorithm 90 (3)
2 Related Work 93 (2)
3 Experimental Results 95 (6)
8. CONCLUSION 101(2)
References 103(4)
Index 107