3D TCAD Simulation for CMOS Nanoeletronic Devices

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3D TCAD Simulation for CMOS Nanoeletronic Devices

  • オンデマンド(OD/POD)版です。キャンセルは承れません。
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  • 製本 Paperback:紙装版/ペーパーバック版/ページ数 330 p.
  • 言語 ENG
  • 商品コード 9789811097799
  • DDC分類 537.622

Full Description

This book demonstrates how to use the Synopsys Sentaurus TCAD 2014 version for the design and simulation of 3D CMOS (complementary metal-oxide-semiconductor) semiconductor nanoelectronic devices, while also providing selected source codes (Technology Computer-Aided Design, TCAD). Instead of the built-in examples of Sentaurus TCAD 2014, the practical cases presented here, based on years of teaching and research experience, are used to interpret and analyze simulation results of the physical and electrical properties of designed 3D CMOSFET (metal-oxide-semiconductor field-effect transistor) nanoelectronic devices.

The book also addresses in detail the fundamental theory of advanced semiconductor device design for the further simulation and analysis of electric and physical properties of semiconductor devices. The design and simulation technologies for nano-semiconductor devices explored here are more practical in nature and representative of the semiconductor industry, and as such can promote the development of pioneering semiconductor devices, semiconductor device physics, and more practically-oriented approaches to teaching and learning semiconductor engineering. 

The book can be used for graduate and senior undergraduate students alike, while also offering a reference guide for engineers and experts in the semiconductor industry. Readers are expected to have some preliminary knowledge of the field.

Contents

Introduction of Synopsys Sentaurus TCAD 2014 version software environment operation interface and tools.- Simulation analysis of 2D MOSFET.- Simulation analysis of 3D FinFET with LG = 15 nm.- Simulation analysis of Inverter and SRAM of 3D FinFET with LG = 15 nm.- Simulation analysis of GAA NWFET.- Simulation analysis of Junctionless FET with LG = 10 nm.- Simulation analysis of Tunnel FET.- Simulation analysis of Si and Ge 3D FinFET with LG = 3 nm.

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