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Full Description
Digital Background Calibration of Analog to Digital Converters takes a deep look at the digital calibration techniques in analog-to-digital converters. The problem of compensating for analog circuits impairments is divided into a system identification problem and an error compensation problem. Different approaches in modelling the analog impairments are discussed. Although Digital Background Calibration of Analog to Digital Converters focuses on two popular types of ADCs mainly: Pipeline and Sigma Delta the techniques can be easily used for any analog and mixed-signal design. Design examples are provided that support the theory and show the application of these techniques in designing high performance data acquisitions systems for wireless communication systems, bio-implantable devices and space electronics.
Contents
List of abbreviations. List of symbols. Preface. 1 Introduction. 1.1 Analog design challenges in deep sub micron technology. 1.2 Motivations for digital calibration in analog-to-digital converters. 1.3 Layout of the book. 2 Digital calibration for Nyquist rate analog-to-digital converters. 2.1 Accuracy limiting factors in ADC. 2.2 Off-line calibration of errors. 2.3 Pseudo-on-line (queue-based) calibration approach. 2.4 Background (correlation-based) calibration techniques. 2.5 Comparison of different calibration approaches. 3 A 14-bit 50 Msps Pipeline ADC equipped with comprehensive calibration engine. 3.1 Introduction. 3.2 Pipeline architecture. 3.3 A comprehensive calibration engine for Pipeline ADC. 3.4 Noise budget. 3.5 Block level specifications. 3.6 Circuit design. 3.7 Physical design and layout. 3.8 Floor Plan. 3.9 Experimental results. 3.10 Conclusion. 4 Digital calibration for oversampling analog-to-digital converters. 4.1 Accuracy limiting factors in oversampling ADCs. 4.2 Discrete-time versus continuous-time implementation. 4.3 MASH versus single loop architectures. 4.4 Noise leakage in MASH Sigma Delta ADCs. 4.5 Digital calibration techniques for discrete-time Sigma Delta converters. 4.6 Digital calibration techniques for continuous-time Sigma Delta converters. 5 A 12-bit 10 MHz MASH Continuous time Sigma Delta ADC with background calibration of errors. 5.1 Introduction. 5.2 Sigma delta ADC architecture. 5.3 Direct synthesis of continuous time modulator. 5.4 Excess loop delay compensation. 5.5 Optimization of design to reduce the effect of clock jitter. 5.6 Calibration for DAC mismatch errors. 5.7 Circuit design. 5.8 Conclusion. 6 Prospects for digitally assisted analog-to-digital converters. 6.1 Compensation for non-deterministic errors. 6.2 Active Noise Cancellation (ANC) techniques. 6.3 Decoupled cancellation of higher order harmonics. 6.4 Conclusion.
