Design, Analysis and Test of Logic Circuits under Uncertainty (Lecture Notes in Electrical Engineering) 〈Vol. 115〉

Krishnaswamy, S./ Markov, I. L./ Hayes, J.

Springer（2012/08発売）

• 製本 Hardcover:ハードカバー版／ページ数 123 p.／サイズ 71 illus.
• 言語 ENG
• 商品コード 9789048196432
• DDC分類 621

Full Description

Logic circuits are becoming increasingly susceptible to probabilistic behavior caused by external radiation and process variation. In addition, inherently probabilistic quantum- and nano-technologies are on the horizon as we approach the limits of CMOS scaling. Ensuring the reliability of such circuits despite the probabilistic behavior is a key challenge in IC design---one that necessitates a fundamental, probabilistic reformulation of synthesis and testing techniques. This monograph will present techniques for analyzing, designing, and testing logic circuits with probabilistic behavior.

Contents

Introduction.- Probabilistic Transfer Matrices.- Computing with Probabilistic Transfer Matrices.- Testing Logic Circuits for Probabilistic Faults.- Signtaure-based Reliability Analysis.- Design for Robustness.- Summary and Extensions.