Full Description
1 2 Per Stenstro ..m and David Whalley 1 Chalmers University of Technology, Sweden 2 Florida State University, U.S.A. In January2007,the secondedition in the series of International Conferenceson High-Performance Embedded Architectures andCompilers (HiPEAC'2007)was held in Ghent,Belgium.We were fortunate to attract around70 submissions of whichonly19wereselected forpresentation.Amongthese,weaskedtheauthors ofthe?vemost highly rated contributionsto make extended versions ofthem. They all accepted to do that andtheirarticles appear in this section ofthe second volume. The?rstarticlebyKeramidas,Xekalakis,andKaxirasfocusesontheincreased power consumption in set-associativecaches.They presenta novel approach to reduce dynamicpower that leverages on the previously proposed cache decay approach that has been shown to reduce static (or leakage) power. In the secondarticlebyMagarajan,Gupta,andKrishnaswamythe focus ison techniques to encrypt data in memory to preservedata integrity. The problem with previous techniques is that the decryption latency ends up on the critical memory access path. Especially in embedded processors,caches are small and it isdi?cultto hide the decryption latency.
The authors propose a compiler-based strategy that manages to reduce the impact of the decryption time signi?cantly. The thirdarticlebyKluyskensandEeckhoutfocusesondetailedarchitectural simulation techniques.It is well-known that they are ine?cientandaremedy to the problem isto use sampling.When usingsampling,onehastowarm up memory structures such as caches andbranch predictors.Thispaper introduces a noveltechnique calledBranchHistoryMatchingfore?cient warmupofbranch predictors. The fourth articlebyBhadauria,McKee,Singh, and Tyson focuses on static power consumptioninlarge caches.Theyintroduce a reuse-distance drowsy cache mechanism that issimpleas well as e?ective in reducingthestaticpower in caches.
Contents
Special Section on High-Performance Embedded Architectures and Compilers.- Recruiting Decay for Dynamic Power Reduction in Set-Associative Caches.- Compiler-Assisted Memory Encryption for Embedded Processors.- Branch Predictor Warmup for Sampled Simulation through Branch History Matching.- Data Cache Techniques to Save Power and Deliver High Performance in Embedded Systems.- Combining Edge Vector and Event Counter for Time-Dependent Power Behavior Characterization.- Regular Papers.- Accurate Instruction Pre-scheduling in Dynamically Scheduled Processors.- Fetch Gating Control through Speculative Instruction Window Weighting.- Fast Code Generation for Embedded Processors with Aliased Heterogeneous Registers.- Linux Kernel Compaction through Cold Code Swapping.- Complexity Effective Bypass Networks.- A Context-Parameterized Model for Static Analysis of Execution Times.- Reexecution and Selective Reuse in Checkpoint Processors.- Compiler Support for Code Size Reduction Using a Queue-Based Processor.- Power-Aware Bus Coscheduling for Periodic Realtime Applications Running on Multiprocessor SoC.- Performance Characterization for the Implementation of Content Addressable Memories Based on Parallel Hashing Memories.
