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Full Description
The demand for ever smaller and portable electronic devices has driven metal oxide semiconductor-based (CMOS) technology to its physical limit with the smallest possible feature sizes. This presents various size-related problems such as high power leakage, low-reliability, and thermal effects, and is a limit on further miniaturization. To enable even smaller electronics, various nanodevices including carbon nanotube transistors, graphene transistors, tunnel transistors and memristors (collectively called post-CMOS devices) are emerging that could replace the traditional and ubiquitous silicon transistor. This book explores these nanoelectronics at the device level including modelling and design.
Topics covered include high-k dielectrics; high mobility n and p channels on gallium arsenide and silicon substrates using interfacial misfit dislocation arrays; anodic metal-insulator-metal (MIM) capacitors; graphene transistors; junction and doping free transistors; nanoscale gigh-k/metal-gate CMOS and FinFET based logic libraries; multiple-independent-gate nanowire transistors; carbon nanotubes for efficient power delivery; timing driven buffer insertion for carbon nanotube interconnects; memristor modeling; and neuromorphic devices and circuits.
This book is essential reading for researchers, research-focused industry designers/developers, and advanced students working on next-generation electronic devices and circuits.
Contents
Chapter 1: High-κ dielectrics and device reliability
Chapter 2: High mobility n and p channels on gallium arsenide and silicon substrates using interfacial misfit dislocation arrays
Chapter 3: Anodic metal-insulator-metal (MIM) capacitors
Chapter 4: Graphene transistors - present and beyond
Chapter 5: Junction and doping-free transistors for future computing
Chapter 6: Nanoscale high-κ/metal-gate CMOS and FinFET based logic libraries
Chapter 7: FinFET and reliability considerations of next-generation processors
Chapter 8: Multiple-independent-gate nanowire transistors: from technology to advanced SoC design
Chapter 9: Exploration of carbon nanotubes for efficient power delivery
Chapter 10: Timing driven buffer insertion for carbon nanotube interconnects
Chapter 11: Memristor modeling - static, statistical, and stochastic methodologies
Chapter 12: Neuromorphic devices and circuits
