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Full Description
examples are presented. These chapters are intended to introduce the reader to the programs. The program structure and models used will be described only briefly. Since these programs are in the public domain (with the exception of the parasitic simulation programs), the reader is referred to the manuals for more details. In this second edition, the process program SUPREM III has been added to Chapter 2. The device simulation program PISCES has replaced the program SIFCOD in Chapter 3. A three-dimensional parasitics simulator FCAP3 has been added to Chapter 4. It is clear that these programs or other programs with similar capabilities will be indispensible for VLSI/ULSI device developments. Part B of the book presents case studies, where the application of simu lation tools to solve VLSI device design problems is described in detail. The physics of the problems are illustrated with the aid of numerical simulations. Solutions to these problems are presented. Issues in state-of-the-art device development such as drain-induced barrier lowering, trench isolation, hot elec tron effects, device scaling and interconnect parasitics are discussed. In this second edition, two new chapters are added. Chapter 6 presents the methodol ogy and significance of benchmarking simulation programs, in this case the SUPREM III program. Chapter 13 describes a systematic approach to investi gate the sensitivity of device characteristics to process variations, as well as the trade-otIs between different device designs.
Contents
Overview.- A : Numerical Simulation Systems.- 1. Numerical Simulation Systems.- 2. Process Simulation.- 3. Device Simulation.- 4. Parasitic Elements Simulation.- B : Applications and Case Studies.- 5. Methodology in Computer-Aided Design for Process and Device Development.- 6. SUPREM III Application.- 7. Simulation Techniques for Advanced Device Development.- 8. Drain-Induced Barrier Lowering in Short Channel Transistors.- 9. A Study of LDD Device Structure Using 2-D Simulations.- 10. The Surface Inversion Problem in Trench Isolated CMOS.- 11. Development of Isolation Structures for Applications in VLSI.- 12. Transistor Design for Submicron CMOS Technology.- 13. A Systematic Study of Transistor Design Trade-offs.- 14. MOSFET Scaling by CADDET.- 15. Examples of Parasitic Elements Simulation.- Source Information of 2-D Programs.- Table of Symbols.- About the Authors.
