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基本説明
Introduces the basics of turbo codes in their different flavors (more specifically, parallel concatenated convolutional turbo codes and block turbo codes).
Full Description
PREFACE The increasing demand on high data rate and quality of service in wireless communication has to cope with limited bandwidth and energy resources. More than 50 years ago, Shannon has paved the way to optimal usage of bandwidth and energy resources by bounding the spectral efficiency vs. signal to noise ratio trade-off. However, as any information theorist, Shannon told us what is the best we can do but not how to do it [1]. In this view, turbo codes are like a dream come true: they allow approaching the theoretical Shannon capacity limit very closely. However, for the designer who wants to implement these codes, at first sight they appear to be a nightmare. We came a huge step closer in striving the theoretical limit, but see the historical axiom repeated on a different scale: we know we can achieve excellent performance with turbo codes, but not how to realize this in real devices.
Contents
1: Turbo CodesIntroducing the communication problem they solve, and the implementation problem they create.- 1.1. A communication and Microelectronics perspective.- 1.2. Turbo codes: desirable channel coding solutions.- 1.3 Conclusions.- 1.4 References.- 2: Design Methodology: The Strategic PlanGetting turbo-codes implemented at maximum performance/cost.- 2.1 Introduction.- 2.2 Algorithmic exploration.- 2.3 Data Transfer and Storage Exploration.- 2.4 From architecture to silicon integration.- 2.5 Conclusions.- 2.6 References.- 3: Conquering the MapRemoving the main bottleneck of convolutional turbo decoders.- 3.1 Introduction.- 3.2 The MAP decoding algorithm for convolutional turbo codes.- 3.3 Simplification of the MAP algorithm: log-max MAP.- 3.5 MAP architecture definition: systematic approach.- 3.6 Conclusions.- 3.7 References.- 4: Demystifying the Fang-Buda AlgorithmBoosting the block turbo decoding.- 4.1. Introduction.- 4.2. Soft decoding of algebraic codes.- 4.3. FBA Optimization and Architecture Derivation.- 4.4. FBA-based BTC decoder performance.- 4.5. Conclusions.- 4.6. References.- 5: Mastering the InterleaverDivide and Conquer.- 5.1. Introduction.- 5.2. Basic elements of the interleaver.- 5.3. Collision-free interleavers.- 5.4. Case study: the 3GPP interleaver and a 3GPP collision-free interleaver.- 5.5. Optimized scheduling for turbo decoding: collision-free interleaving and deinterleaving.- 5.6. References.- 6: T@MPO CodecFrom theory to real life silicon.- 6.1. Introduction.- 6.2. Positioning oneself in the optimal performance-speed-cost space.- 6.3. Design flow.- 6.4. Decoder final architecture.- 6.5. Synthesis results.- 6.6. Measurements results.- 6.7. T@MPO features.- 6.8. References.- Abbreviations list.- Symbol list.
