DSP System Design : Complexity Reduced Iir Filter Implementation for Practical Applications

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DSP System Design : Complexity Reduced Iir Filter Implementation for Practical Applications

  • ウェブストア価格 ¥23,849(本体¥21,681)
  • Kluwer Academic Pub(2003/09発売)
  • 外貨定価 US$ 109.99
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  • ポイント 1,080pt
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  • 製本 Hardcover:ハードカバー版/ページ数 246 p.
  • 言語 ENG
  • 商品コード 9781402075582
  • DDC分類 621.3822

基本説明

Presents the investigation of special type of IIR polyphase filter structures combined with frequency transformation techniques used for fast, multi-rate filtering, and their application for custom fixed-point implementation.

Full Description

This text presents the investigation of special type of IIR polyphase filter structures combined with frequency transformation techniques used for fast, multi-rate filtering, and their application for custom fixed-point implementation. Detailed theoretical analysis of the polyphase IIR structure has been presented for two and three coefficients in the two-path arrangement. This was then generalized for arbitrary filter order and any number of paths. The use of polyphase IIR structures in decimation and interpolation is being presented and performance assessed in terms of the number of calculations required for the given filter specification and the simplicity of implementation. Specimen decimation filter designs to be used in Sigma-Delta lowpass and bandpass A/D converters are presented which prove to outperform other traditional approaches. New frequency transformation types have been suggested for both real and complex situations. A new exact multi-point frequency transformation approach for arbitrary frequency choice has been suggested and evaluated.
Applying such transformations to the existing filter allows them to change their frequency response in an intuitive manner without the need of re-designing them, thus simplifying the designer's job when the specification changes during the prototyping and testing. A new "bit-flipping" algorithm has been developed to aid in filter design where the coefficient word length is constraint. Also, the standard Downhill Simplex Method (floating-point) was modified to operate with the constrained coefficient word length. Performance of both these advances is being evaluated on a number of filter cases. Novel decimation and interpolation structures have been proposed, which can be implemented very efficiently. These allow an arbitrary order IIR anti-aliasing filter to operate at the lower rate of the decimator/interpolator. Similar structures for polyphase IIR decimator/interpolator structures are being discussed too. A new approach to digital filter design and implementation has been suggested which speeds-up silicon implementation of designs developed in Matlab. The Simulink block description is converted automatically into a bit-to-bit equivalent VHDL description.
This in turn can be compiled, simulated, synthesized and fabricated without the need to go through the design process twice, first algorithmic/structural design and then the implementation.

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