Writing Testbenches : Functional Verification of HDL Models （2ND）

Bergeron, Janick

Springer（2003発売）

• 製本 Hardcover:ハードカバー版／ページ数 512 p.
• 言語 ENG
• 商品コード 9781402074011

基本説明

Presents the verification techniques to produce fully functional first silicon ASICs, systems-on-a-chip (SoC), boards and entire systems. New Topics: Discussions on OpenVera and e; strategies for making testbenches self-checking; VHDL and Verilog language semantics...

Full Description

This second edition presents the most up-to-date verification techniques to produce fully functional first silicon ASICs, systems-on-a-chip (SoC), boards and entire systems. Topics included are: discussions on openvera and e; approaches for writing constrainable random stimulus generators; strategies for making testbenches self-checking; a clear blueprint of a verification process that aims for first time success; recent advances in functional verification such as coverage-driven verification process; VHDL and Verilog language semantics; the semantics are presented in new verification-oriented languages; techniques for applying stimulus and monitoring the response of a design; behavioural modelling using non-synthesizeable constructs and coding style; and updated for Verilog 2001.