Computer Systems : An Embedded Approach

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Computer Systems : An Embedded Approach

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  • 製本 Hardcover:ハードカバー版/ページ数 548 p.
  • 言語 ENG,ENG
  • 商品コード 9781260117608
  • DDC分類 621

Full Description


Incorporate embedded computing technology in projects and devices of all sizesThis comprehensive engineering textbook lays out foundational computer architecture principles and teaches, step by step, how to apply those concepts in cutting-edge embedded applications. The book includes everything you need to know about embedded computing-from fundamentals and processor internals to networking and connectivity.Computer Systems: An Embedded Approach begins by thoroughly explaining constituent hardware components, including processors, storage devices, and accelerators. From there, the book shows how operating systems work and how they provide a layer of services between hardware and software. You will get coverage of foundational networking, pervasive computing concepts, and the Internet of Things (IoT). The book concludes with a look to the future of embedded computing systems.*This single resource takes readers right up to being ready to learn programming*Covers code aspects from the IEEE, POSIX, and OSI models *Written by a recognized academic and experienced authorNER(01): WOW

Table of Contents

Preface                                            xvii
Acknowledgments xxi
List of Boxes xxiii
1 Introduction 1 (16)
1.1 The Evolution of Computers 1 (2)
1.2 Forward Progress 3 (2)
1.3 Computer Generations 5 (7)
1.3.1 First Generation 6 (1)
1.3.2 Second Generation 7 (1)
1.3.3 Third Generation 8 (1)
1.3.4 Fourth Generation 9 (1)
1.3.5 Fifth Generation 10 (2)
1.4 Cloud, Pervasive, Grid, and Massively 12 (1)
Parallel Computers
1.5 Where To from Here? 13 (3)
1.6 Summary 16 (1)
2 Foundations 17 (52)
2.1 Computer Organization 17 (4)
2.1.1 Flynn's Taxonomy 18 (1)
2.1.2 Connection Arrangements 18 (2)
2.1.3 Layered View of Computer Organization 20 (1)
2.2 Computer Fundamentals 21 (4)
2.3 Number Formats 25 (6)
2.3.1 Unsigned Binary 26 (1)
2.3.2 Sign Magnitude 26 (1)
2.3.3 One's Complement 27 (1)
2.3.4 Two's Complement 27 (1)
2.3.5 Excess-n 28 (1)
2.3.6 Binary-Coded Decimal 29 (1)
2.3.7 Fractional Notation 29 (1)
2.3.8 Sign Extension 30 (1)
2.4 Arithmetic 31 (6)
2.4.1 Addition 32 (1)
2.4.2 The Parallel Carry-Propagate Adder 32 (2)
2.4.3 Carry Look-Ahead 34 (1)
2.4.4 Subtraction 35 (2)
2.5 Multiplication 37 (7)
2.5.1 Repeated Addition 38 (1)
2.5.2 Partial Products 38 (4)
2.5.3 Shift-Add Method 42 (1)
2.5.4 Booth's and Robertson's 42 (2)
Methods
2.6 Division 44 (2)
2.6.1 Repeated Subtraction 44 (2)
2.7 Working with Fractional Number Formats 46 (3)
2.7.1 Arithmetic with Fractional Numbers 47 (1)
2.7.2 Multiplication and Division of 48 (1)
Fractional Numbers
2.8 Floating Point 49 (9)
2.8.1 Generalized Floating Point 49 (1)
2.8.2 IEEE754 Floating Point 50 (1)
2.8.3 IEEE754 Modes 51 (4)
2.8.4 IEEE754 Number Ranges 55 (3)
2.9 Floating Point Processing 58 (6)
2.9.1 Addition and Subtraction of IEEE754 59 (3)
Numbers
2.9.2 Multiplication and Division of 62 (1)
IEEE754 Numbers
2.9.3 IEEE754 Intermediate Formats 62 (1)
2.9.4 Rounding 63 (1)
2.10 Summary 64 (1)
2.11 Problems 64 (5)
3 CPU Basics 69 (54)
3.1 What Is a Computer? 69 (1)
3.2 Making the Computer Work for You 70 (16)
3.2.1 Program Storage 70 (1)
3.2.2 Memory Hierarchy 71 (2)
3.2.3 Program Transfer 73 (1)
3.2.4 Control Unit 74 (5)
3.2.5 Microcode 79 (2)
3.2.6 RISC versus CISC Approaches 81 (2)
3.2.7 Example Processor-the ARM 83 (2)
3.2.8 More about the ARM 85 (1)
3.3 Instruction Handling 86 (16)
3.3.1 The Instruction Set 86 (4)
3.3.2 Instruction Fetch and Decode 90 (5)
3.3.3 Compressed Instruction Sets 95 (2)
3.3.4 Addressing Modes 97 (4)
3.3.5 Stack Machines and Reverse Polish 101 (1)
Notation
3.4 Data Handling 102 (11)
3.4.1 Data Formats and Representations 103 (4)
3.4.2 Data Flows 107 (1)
3.4.3 Data Storage 107 (1)
3.4.4 Internal Data 108 (1)
3.4.5 Data Processing 109 (4)
3.5 A Top-Down View 113 (5)
3.5.1 Computer Capabilities 113 (1)
3.5.2 Performance Measures, Statistics, and 114 (2)
Lies
3.5.3 Assessing Performance 116 (2)
3.6 Summary 118 (1)
3.7 Problems 119 (4)
4 Processor Internals 123 (50)
4.1 Internal Bus Architecture 123 (9)
4.1.1 A Programmer's Perspective 123 (1)
4.1.2 Split Interconnection Arrangements 124 (2)
4.1.3 ADSP21xx Bus Arrangement 126 (1)
4.1.4 Simultaneous Data and Program Memory 127 (2)
Access
4.1.5 Dual-Bus Architectures 129 (2)
4.1.6 Single-Bus Architectures 131 (1)
4.2 Arithmetic Logic Unit 132 (4)
4.2.1 ALU Functionality 132 (1)
4.2.2 ALU Design 133 (3)
4.3 Memory Management Unit 136 (8)
4.3.1 The Need for Virtual Memory 136 (1)
4.3.2 MMU Operation 136 (3)
4.3.3 Retirement Algorithms 139 (1)
4.3.4 Internal Fragmentation and 140 (1)
Segmentation
4.3.5 External Fragmentation 140 (2)
4.3.6 Advanced MMUs 142 (1)
4.3.7 Memory Protection 143 (1)
4.4 Cache 144 (14)
4.4.1 Direct Cache 146 (2)
4.4.2 Set-Associative Cache 148 (1)
4.4.3 Full-Associative Caches 149 (1)
4.4.4 Locality Principles 149 (1)
4.4.5 Cache Replacement Algorithms 150 (4)
4.4.6 Cache Performance 154 (2)
4.4.7 Cache Coherency 156 (2)
4.5 Coprocessors 158 (1)
4.6 Floating Point Unit 159 (3)
4.6.1 Floating Point Emulation 160 (2)
4.7 Streaming SIMD Extensions and Multimedia 162 (3)
Extensions
4.7.1 Multimedia Extensions 162 (1)
4.7.2 MMX Implementation 163 (1)
4.7.3 Use of MMX 164 (1)
4.7.4 Streaming SIMD Extensions 164 (1)
4.7.5 Using SSE and MMX 165 (1)
4.8 Coprocessing in Embedded Systems 165 (2)
4.9 Summary 167 (1)
4.10 Problems 167 (6)
5 Enhancing CPU Performance 173 (82)
5.1 Speedups 174 (1)
5.2 Pipelining 174 (19)
5.2.1 Multifunction Pipelines 176 (1)
5.2.2 Dynamic Pipelines 177 (1)
5.2.3 Changing Mode in a Pipeline 178 (2)
5.2.4 Data Dependency Hazard 180 (1)
5.2.5 Conditional Hazards 181 (2)
5.2.6 Conditional Branches 183 (2)
5.2.7 Compile-Time Pipeline Remedies 185 (2)
5.2.8 Relative Branching 187 (1)
5.2.9 Instruction Set Pipeline Remedies 188 (1)
5.2.10 Run-Time Pipeline Remedies 189 (4)
5.3 Complex and Reduced Instruction Set 193 (1)
Computers
5.4 Superscalar Architectures 194 (4)
5.4.1 Simple Superscalar 194 (3)
5.4.2 Multiple-Issue Superscalar 197 (1)
5.4.3 Superscalar Performance 197 (1)
5.5 Instructions per Cycle 198 (3)
5.5.1 IPC of Difference Architectures 198 (2)
5.5.2 Measuring IPC 200 (1)
5.6 Hardware Acceleration 201 (7)
5.6.1 Zero-Overhead Loops 201 (3)
5.6.2 Address Handling Hardware 204 (3)
5.6.3 Shadow Registers 207 (1)
5.7 Branch Prediction 208 (19)
5.7.1 The Need for Branch Prediction 209 (2)
5.7.2 Single T-Bit Predictor 211 (1)
5.7.3 Two-Bit Predictor 212 (2)
5.7.4 The Counter and Shift Registers as 214 (1)
Predictors
5.7.5 Local Branch Predictor 214 (3)
5.7.6 Global Branch Predictor 217 (2)
5.7.7 The Gselect Predictor 219 (2)
5.7.8 The Gshare Predictor 221 (1)
5.7.9 Hybrid Predictors 222 (2)
5.7.10 Branch Target Buffer 224 (1)
5.7.11 Basic Blocks 225 (2)
5.7.12 Branch Prediction Summary 227 (1)
5.8 Parallel and Massively Parallel Machines 227 (12)
5.8.1 Evolution of SISD to MIMD 230 (2)
5.8.2 Parallelism for Raw Performance 232 (2)
5.8.3 More on Parallel Processing 234 (5)
5.9 Tomasulo's Algorithm 239 (7)
5.9.1 The Rationale behind Tomasulo's 239 (1)
Algorithm
5.9.2 An Example Tomasulo System 240 (5)
5.9.3 Tomasulo in Embedded Systems 245 (1)
5.10 Very Long Instruction Word Architectures 246 (4)
5.10.1 What Is VLIW? 246 (2)
5.10.2 The VLIW Rationale 248 (1)
5.10.3 Difficulties with VLIW 249 (1)
5.10.4 Comparison with Superscalar 250 (1)
5.11 Summary 250 (1)
5.12 Problems 251 (4)
6 Externals 255 (36)
6.1 Interfacing Using a Bus 255 (3)
6.1.1 Bus Control Signals 256 (1)
6.1.2 Direct Memory Access 257 (1)
6.2 Parallel Bus Specifications 258 (2)
6.3 Standard Interfaces 260 (9)
6.3.1 System Control Interfaces 260 (1)
6.3.2 System Data Buses 260 (7)
6.3.3 I/O Buses 267 (1)
6.3.4 Peripheral Device Buses 267 (1)
6.3.5 Interface to Networking Devices 268 (1)
6.4 Real-Time Issues 269 (4)
6.4.1 External Stimuli 269 (1)
6.4.2 Interrupts 269 (1)
6.4.3 Real-Time Definitions 270 (1)
6.4.4 Temporal Scope 270 (2)
6.4.5 Hardware Architecture Support for 272 (1)
Real Time
6.5 Interrupts and Interrupt Handling 273 (9)
6.5.1 The Importance of Interrupts 274 (1)
6.5.2 The Interrupt Process 274 (6)
6.5.3 Advanced Interrupt Handling 280 (1)
6.5.4 Sharing Interrupts 280 (1)
6.5.5 Reentrant Code 281 (1)
6.5.6 Software Interrupts 281 (1)
6.6 Embedded Wireless Connectivity 282 (3)
6.6.1 Wireless Technology 282 (2)
6.6.2 Wireless Interfacing 284 (1)
6.6.3 Issues Relating to Wireless 284 (1)
6.7 Summary 285 (1)
6.8 Problems 285 (6)
7 Practical Embedded CPUs 291 (80)
7.1 Introduction 291 (1)
7.2 Microprocessors Are Core Plus More 291 (4)
7.3 Required Functionality 295 (3)
7.4 Clocking 298 (3)
7.4.1 Clock Generation 300 (1)
7.5 Clocks and Power 301 (5)
7.5.1 Propagation Delay 303 (1)
7.5.2 The Trouble with Current 303 (1)
7.5.3 Solutions for Clock Issues 304 (1)
7.5.4 Low-Power Design 304 (2)
7.6 Memory 306 (15)
7.6.1 Early Computer Memory 306 (1)
7.6.2 ROM: Read-Only Memory 307 (7)
7.6.3 RAM: Random-Access Memory 314 (7)
7.7 Pages and Overlays 321 (2)
7.8 Memory in Embedded Systems 323 (5)
7.8.1 Booting from Non-Volatile Memory 325 (2)
7.8.2 Other Memory 327 (1)
7.9 Test and Verification 328 (8)
7.9.1 IC Design and Manufacture Problems 328 (3)
7.9.2 Built-In Self-Test 331 (2)
7.9.3 JTAG 333 (3)
7.10 Error Detection and Correction 336 (4)
7.11 Watchdog Timers and Reset Supervision 340 (3)
7.11.1 Reset Supervisors and Brownout 341 (2)
Detectors
7.12 Reverse Engineering 343 (10)
7.12.1 The Reverse Engineering Process 344 (4)
7.12.2 Detailed Physical Layout 348 (5)
7.13 Preventing Reverse Engineering 353 (5)
7.13.1 Passive Obfuscation of Stored 355 (1)
Programs
7.13.2 Programmable Logic Families 356 (1)
7.13.3 Active RE Mitigation 357 (1)
7.13.4 Active RE Mitigation Classification 357 (1)
7.14 Soft Core Processors 358 (5)
7.14.1 Microprocessors Are More Than Cores 359 (1)
7.14.2 The Advantages of Soft Core 360 (3)
Processors
7.15 Hardware Software Codesign 363 (2)
7.16 Off-the-Shelf Cores 365 (2)
7.17 Summary 367 (1)
7.18 Problems 368 (3)
8 Programming 371 (20)
8.1 Running a Program 372 (4)
8.1.1 What Does Executing Mean? 372 (3)
8.1.2 Other Things to Note 375 (1)
8.2 Writing a Program 376 (7)
8.2.1 Compiled Languages 377 (4)
8.2.2 Interpreted Languages 381 (2)
8.3 The UNIX Programming Model 383 (5)
8.3.1 The Shell 384 (1)
8.3.2 Redirections and Data Flow 385 (2)
8.3.3 Utility Software 387 (1)
8.4 Summary 388 (1)
8.5 Problems 388 (3)
9 Operating Systems 391 (46)
9.1 What Is an Operating System? 391 (1)
9.2 Why Do We Need an Operating System? 392 (4)
9.2.1 Operating System Characteristics 393 (1)
9.2.2 Types of Operating Systems 394 (2)
9.3 The Role of an Operating System 396 (6)
9.3.1 Resource Management 396 (1)
9.3.2 Virtual Machine 396 (1)
9.3.3 CPU Time 397 (1)
9.3.4 Memory Management 398 (2)
9.3.5 Storage and Filing 400 (1)
9.3.6 Protection and Error Handling 401 (1)
9.4 OS Structure 402 (3)
9.4.1 Layered Operating Systems 403 (1)
9.4.2 Client-Server Operating Systems 404 (1)
9.5 Booting 405 (5)
9.5.1 Booting from Parallel Flash 406 (2)
9.5.2 Booting from HDD/SSD 408 (1)
9.5.3 What Happens Next 409 (1)
9.6 Processes 410 (3)
9.6.1 Processes, Processors, and Concurrency 411 (2)
9.7 Scheduling 413 (4)
9.7.1 The Scheduler 414 (3)
9.8 Storage and File Systems 417 (16)
9.8.1 Secondary Storage 417 (4)
9.8.2 Need for File Systems 421 (3)
9.8.3 What Are File Systems? 424 (7)
9.8.4 Backup 431 (2)
9.9 Summary 433 (1)
9.10 Problems 434 (3)
10 Connectivity 437 (24)
10.1 Why Connect, How to Connect 437 (6)
10.1.1 One-to-One Communications 438 (1)
10.1.2 One-to-Many Communications 439 (1)
10.1.3 Packet Switching 440 (1)
10.1.4 Simple Communications Topologies 441 (2)
10.2 System Requirements 443 (10)
10.2.1 Packetization 443 (2)
10.2.2 Encoding and Decoding 445 (1)
10.2.3 Transmission 445 (1)
10.2.4 Receiving 445 (1)
10.2.5 Error Handling 446 (5)
10.2.6 Connection Management 451 (2)
10.3 Scalability, Efficiency, and Reuse 453 (1)
10.4 OSI Layers 454 (1)
10.5 Topology and Architecture 455 (3)
10.5.1 Hierarchical Network 455 (1)
10.5.2 Client-Server Architecture 456 (1)
10.5.3 Peer-to-Peer Architecture 456 (1)
10.5.4 Ad Hoc Connection 457 (1)
10.5.5 Mobility and Handoff 458 (1)
10.6 Summary 458 (1)
10.7 Problems 459 (2)
11 Networking 461 (32)
11.1 The Internet 461 (3)
11.1.1 Internet History 462 (1)
11.1.2 Internet Governance 462 (2)
11.2 TCP/IP and the IP Layer Model 464 (5)
11.2.1 Encapsulation 465 (4)
11.3 Ethernet Overview 469 (5)
11.3.1 Ethernet Data Format 470 (1)
11.3.2 Ethernet Encapsulation 471 (2)
11.3.3 Ethernet Carrier Sense 473 (1)
11.4 The Internet Layer 474 (8)
11.4.1 IP Address 474 (2)
11.4.2 Internet Packet Format 476 (1)
11.4.3 Routing 477 (1)
11.4.4 Unicasting and Multicasting 478 (1)
11.4.5 Anycasting 478 (1)
11.4.6 Naming 478 (1)
11.4.7 Domain Name Servers 479 (3)
11.5 The Transport Layer 482 (3)
11.5.1 Port Number 482 (1)
11.5.2 User Datagram Protocol 483 (1)
11.5.3 Transmission Control Protocol 483 (1)
11.5.4 UDP versus TCP 484 (1)
11.6 Other Messages 485 (1)
11.6.1 Address Resolution Protocol 485 (1)
11.6.2 Control Messages 486 (1)
11.7 Wireless Connectivity 486 (4)
11.7.1 WiFi 487 (1)
11.7.2 WiMax 487 (1)
11.7.3 Bluetooth 488 (1)
11.7.4 ZigBee 488 (1)
11.7.5 Near-Field Communications 489 (1)
11.8 Network Scales 490 (1)
11.9 Summary 490 (1)
11.10 Problems 490 (3)
12 The Future 493 (28)
12.1 Single-Bit Architectures 494 (3)
12.1.1 Bit-Serial Addition 494 (1)
12.1.2 Bit-Serial Subtraction 495 (1)
12.1.3 Bit-Serial Logic and Processing 496 (1)
12.2 More-Parallel Machines 497 (8)
12.2.1 Clusters of Small CPUs 497 (4)
12.2.2 Parallel and Cluster Processing 501 (1)
Considerations
12.2.3 Interconnection Strategies 502 (3)
12.3 Asynchronous Processors 505 (4)
12.3.1 Data Flow Control 507 (1)
12.3.2 Avoiding Pipeline Hazards 508 (1)
12.4 Alternative Number Format Systems 509 (5)
12.4.1 Multiple-Valued Logic 509 (1)
12.4.2 Signed Digit Number Representation 510 (4)
12.5 Optical Computation 514 (3)
12.5.1 The Electro-Optical Full Adder 514 (1)
12.5.2 The Electro-Optic Backplane 515 (2)
12.6 Science Fiction or Future Reality? 517 (2)
12.6.1 Distributed Computing 518 (1)
12.6.2 Wetware 518 (1)
12.7 Summary 519 (2)
A Standard Memory Size Notation 521 (2)
B Standard Logic Gates 523 (2)
Index 525