CMOS位相同期回路設計（テキスト） Design of CMOS Phase-Locked Loops : From Circuit Level to Architecture Level

Razavi, Behzad

Cambridge University Press（2020/01発売）

Cambridge University Press（2020/01発売）

• 製本 Hardcover:ハードカバー版／ページ数 506 p.
• 言語 ENG
• 商品コード 9781108494540
• DDC分類 621.3815

Full Description

Using a modern, pedagogical approach, this textbook gives students and engineers a comprehensive and rigorous knowledge of CMOS phase-locked loop (PLL) design for a wide range of applications. It features intuitive presentation of theoretical concepts, built up gradually from their simplest form to more practical systems; broad coverage of key topics, including oscillators, phase noise, analog PLLs, digital PLLs, RF synthesizers, delay-locked loops, clock and data recovery circuits, and frequency dividers; tutorial chapters on high-performance oscillator design, covering fundamentals to advanced topologies; and extensive use of circuit simulations to teach design mentality, highlight design flaws, and connect theory with practice. Including over 200 thought-provoking examples highlighting best practices and common pitfalls, 250 end-of-chapter homework problems to test and enhance the readers' understanding, and solutions and lecture slides for instructors, this is the perfect text for senior undergraduate and graduate-level students and professional engineers who want an in-depth understanding of PLL design.

Contents

1. Oscillator fundamentals; 2. Introduction to jitter and phase noise; 3. Design of inverter-based ring oscillators; 4. Design of differential and multiphase ring oscillators; 5. LC oscillator design; 6. Advanced oscillator concepts; 7. Basic PLL architectures; 8. PLL design considerations; 9. PLL design study; 10. Digital phase-locked loops; 11. Delay-locked loops; 12. RF synthesis; 13. Clock and data recovery fundamentals; 14. Advanced clock and data recovery principles; 15. Frequency dividers.