CMOS and Beyond : Logic Switches for Terascale Integrated Circuits

個数:
電子版価格
¥10,271
  • 電子版あり

CMOS and Beyond : Logic Switches for Terascale Integrated Circuits

  • 提携先の海外書籍取次会社に在庫がございます。通常3週間で発送いたします。
    重要ご説明事項
    1. 納期遅延や、ご入手不能となる場合が若干ございます。
    2. 複数冊ご注文の場合は、ご注文数量が揃ってからまとめて発送いたします。
    3. 美品のご指定は承りかねます。

    ●3Dセキュア導入とクレジットカードによるお支払いについて
  • 【入荷遅延について】
    世界情勢の影響により、海外からお取り寄せとなる洋書・洋古書の入荷が、表示している標準的な納期よりも遅延する場合がございます。
    おそれいりますが、あらかじめご了承くださいますようお願い申し上げます。
  • ◆画像の表紙や帯等は実物とは異なる場合があります。
  • ◆ウェブストアでの洋書販売価格は、弊社店舗等での販売価格とは異なります。
    また、洋書販売価格は、ご注文確定時点での日本円価格となります。
    ご注文確定後に、同じ洋書の販売価格が変動しても、それは反映されません。
  • 製本 Hardcover:ハードカバー版/ページ数 436 p.
  • 言語 ENG
  • 商品コード 9781107043183
  • DDC分類 621.395

Full Description

Get up to speed with the future of logic switch design with this indispensable overview of the most promising successors to modern CMOS transistors. Learn how to overcome existing design challenges using novel device concepts, presented using an in-depth, accessible, tutorial-style approach. Drawing on the expertise of leading researchers from both industry and academia, and including insightful contributions from the developers of many of these alternative logic devices, new concepts are introduced and discussed from a range of different viewpoints, covering all the necessary theoretical background and developmental context. Covering cutting-edge developments with the potential to overcome existing limitations on transistor performance, such as tunneling field-effect transistors (TFETs), alternative charge-based devices, spin-based devices, and more exotic approaches, this is essential reading for academic researchers, professional engineers, and graduate students working with semiconductor devices and technology.

Contents

1. Energy-efficiency limits of digital circuits based on CMOS transistors Elad Alon; 2. Beyond transistor scaling: alternative device structures for the terascale regime Zachery A. Jacobson and Kelin J. Kuhn; 3. Benchmarking alternative device structures for the terascale regime Zachery A. Jacobson and Kelin J. Kuhn; 4. Extending CMOS with negative capacitance Asif Islam Khan and Sayeef Salahuddin; 5. Designing a low voltage, high current tunneling transistor Sapan Agarwal and Eli Yablonovitch; 6. Tunnel transistors Alan Seabaugh, Zhengping Jiang and Gerhard Klimeck; 7. Graphene and 2D crystal tunnel transistors Qin Zhang, Pei Zhao, Nan Ma, Grace (Huili) Xing and Debdeep Jena; 8. Bilayer pseudospin field effect transistor Sanjay Bannerjee, Frank Register and Dharmendar Reddy; 9. Computation and learning with metal-insulator transitions and emergent phases in correlated oxides You Zhou, Sieu D. Ha and Shriram Ramanathan; 10. The piezo-electronic transistor Paul M. Solomon, Bruce G. Elmegreen, Matt Copel, Marcelo A. Kuroda, Susan Trolier-McKinstry, Glenn J. Martyna and Dennis M. Newns; 11. Mechanical switches Tsu-Jae King Liu and Rhesa Nathanael; 12. Nanomagnetic logic: from magnetic ordering to magnetic computing György Csaba, Gary H. Bernstein, Alexei Orlov, Michael T. Niemier, X. Sharon Hu and Wolfgang Porod; 13. Spin torque majority gate logic Dmitri E. Nikonov and George I. Bourianoff; 14. Spin wave phase logic Alexander Khitun; 15. Interconnect considerations Ahmet Ceyhan, Shaloo Rakheja and Azad Naeemi.

最近チェックした商品