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基本説明
Reprinted from Journal of VLSE Signal Processing, 5: 2-3
Full Description
Due to the progress in VLSI technology, integrated circuit chips are now available that allow video/image signal processing to be performed with a single VLSI chip or small sets of VLSI chips. Recent standardization on bandwidth compression schemes for still images (JPEG) and motion pictures (H.261, R723, MPEG) also encourage the development of VLSI video/image processors for cost-effective solutions. Furthermore, recent trends suggest that the standardization on HDTB bandwidth compression for broadcasting and storage purposes is just around the corner.
In terms of device technology, however, the progress achieved in increasing speed is not as high as that achieved by integration. The development of high speed systems is due to architectural effort, rather than device technology. This is why high speed architectures, such as those for special wired logic realization and for multi-processors are of great interest to VLSI system designers.
VLSI Video/Image Signal Processing is an edited volume of original research comprising invited contributions by leading researchers.
Contents
Introduction; T. Nishitani, P.H. Ang, F. Catthoor. VLSI in Picture Coding; T. Ishiguro. Single-Chip Image Sensors with a Digital Processor Array; R. Forchheimer, Keping Chen, C. Svensson, A. Odmark. An Image Processing System using Signal Multiprocessors (ISMPs); H. Nakahira, M. Maruyama, H. Ueda, H. Yamada. A Video-Rate JPEG Chip Set; P.A. Ruetz, Po Tong, D. Luthi, P.H. Ang. DCT/IDCT Processor for HDTV developed with DSP Silicon Compiler; T. Miyazaki, T. Nishitani, M. Edahiro, I. Onon, K. Mitsuhashi. A VLSI Based MIMD Architecture of a Multiprocessor System for Real-Time Video Processing Applications; K. Gaedke, H. Jeschke, P. Pirsch. Design of a Processing Board for a Programmable Multi-VSP System; M. Engels, R. Lauwereins, J.A. Peperstraete, A. van Roermund. A VLSI Neuroprocessor for Image Restoration using Analog Computing-Based Systolic Architecture; Ji-Chen Lee, B.J. Sheu, R. Chellappa. Architectural Strategies for High-Throughput Applications; J. van Meerbergen, P. Lippens, B. McSweeney, W. Verhaegh, A. van der Werf, A. van Zanten. An Application-Specific Architecture for the RBN-Code with Efficient Memory Organization; T. Gijbels, F. Catthoor, L. Van Eycken, A. Oosterlinck, H. De Man. System Considerations and the System Level Design of a Chip Set for Real Time TV and HDTV; C.V. Reventlow, M. Talmi, S. Wolf, M. Ernst, K. Muller, C. Stoffers. Systolic Architectures for Finite-State Vector Quantization; R.K. Kolagotla, Shu-Sun Yu, J.F. JaJa. Parallel Implementation for Iterative Image Restoration Algorithms on a Parallel DSP Machine; R.L. Stevenson, G.B. Adams III, L.H. Jamieson, E.J. Delp. An Optimization Technique for Lowering the Iteration Bound of DSP Programs; F. Buchholz Maciel, Y. Miyanaga, K. Tochinai. Subject Index.
