SystemVerilog for Verification : A Guide to Learning the Testbench Language Features （2ND）

Spear, C.

Springer（2008/07発売）

• 製本 Hardcover:ハードカバー版／ページ数 465 p.／サイズ 5 illus.
• 言語 ENG
• 商品コード 9780387765297
• DDC分類 621

Full Description

The updated second edition of this book provides practical information for hardware and software engineers using the SystemVerilog language to verify electronic designs. The author explains methodology concepts for constructing testbenches that are modular and reusable. The book includes extensive coverage of the SystemVerilog 3.1a constructs such as classes, program blocks, randomization, assertions, and functional coverage. This second edition contains a new chapter that covers programs and interfaces as well as chapters with updated information on directed testbench and OOP, layered, and random testbench for an ATM switch.

Contents

Verification Guidelines.- Data Types.- Procedural Statements and Routines.- Connecting the Testbench and Design.- Basic OOP.- Randomization.- Threads and Interprocess Communication.- Advanced OOP and Testbench Guidelines.- Functional Coverage.- Advanced Interfaces.- A Complete SystemVerilog Testbench.- Interfacing with C.