認証のためのＳｙｓｔｅｍ Ｖｅｒｉｌｏｇ SystemVerilog for Verification : A Guide to Learning the Testbench Language Features

Spear, Christian B.

Springer（2008/06発売）

• 製本 Hardcover:ハードカバー版／ページ数 350 p.
• 言語 ENG
• 商品コード 9780387270364

基本説明

Features: Provides extensive coverage of system verilog contructs such as object oriented programming, randomization, and functional coverage; Builds on Verilog 1009 and 2001 codes.

Full Description

"SystemVerilog for Verification" provides practical information for hardware and software engineers using the SystemVerilog language to verify electronic designs. The authors explain methodology concepts for constructing testbenches that are modular and reusable. The book includes extensive coverage of the SystemVerilog 3.1a constructs such as classes, program blocks, randomization, assertions, and functional coverage. It also reviews SystemVerilog 3.0 topics such as interfaces and data types. For hardware engineers, the book has several chapters with detailed explanations of Object Oriented Programming based on years of teaching OOP to hundreds of students. For software engineers, there is a wealth of information on testbenches, multithreaded code, and interfacing to hardware designs. The reader only needs to know the Verilog 1995 standard.

Contents

Verification guidelines.- Data types.- Procedural statements and routines.- Basic OOP.- Connecting the testbench and design.- Randomization.- Threads and interprocess communication.- Advanced OOP and guidelines.- Functional coverage.- Advanced interfaces.- References.- Index.