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Foreword by Joungho KimThe Hands-On Guide to Power Integrity in Advanced Applications, from Three Industry ExpertsIn this book, three industry experts introduce state-of-the-art power integrity design techniques for today's most advanced digital systems, with real-life, system-level examples. They introduce a powerful approach to unifying power and signal integrity design that can identify signal impediments earlier, reducing cost and improving reliability.After introducing high-speed, single-ended and differential I/O interfaces, the authors describe on-chip, package, and PCB power distribution networks (PDNs) and signal networks, carefully reviewing their interactions. Next, they walk through end-to-end PDN and signal network design in frequency domain, addressing crucial parameters such as self and transfer impedance. They thoroughly address modeling and characterization of on-chip components of PDNs and signal networks, evaluation of power-to-signal coupling coefficients, analysis of Simultaneous Switching Output (SSO) noise, and many other topics.Coverage includes* The exponentially growing challenge of I/O power integrity in high-speed digital systems* PDN noise analysis and its timing impact for single-ended and differential interfaces* Concurrent design and co-simulation techniques for evaluating all power integrity effects on signal integrity* Time domain gauges for designing and optimizing components and systems* Power/signal integrity interaction mechanisms, including power noise coupling onto signal trace and noise amplification through signal resonance* Performance impact due to Inter Symbol Interference (ISI), crosstalk, and SSO noise, as well as their interactions* Validation techniques, including low impedance VNA measurements, power noise measurements, and characterization of power-to-signal coupling effectsPower Integrity for I/O Interfaces will be an indispensable resource for everyone concerned with power integrity in cutting-edge digital designs, including system design and hardware engineers, signal and power integrity engineers, graduate students, and researchers.
Contents
Foreword by Joungho Kim xiiiPreface xvAbout the Authors xxiChapter 1 Introduction 11.1 Digital Electronic System 11.2 I/O Signaling Standards 21.2.1 Single-Ended and Differential Signaling 31.3 Power and Signal Distribution Network 51.4 Signal and Power Integrity 61.5 Power Noise to Signal Coupling 81.5.1 SSO 91.5.2 Chip-Level SSO Coupling 91.5.3 Interconnect Level SSO Coupling 101.6 Concurrent Design Methodology 12References 13Chapter 2 I/O Interfaces 152.1 Single-Ended Drivers and Receivers 152.1.1 Open Drain Drivers 162.1.2 Push-Pull Driver and Receiver 172.1.3 Termination Schemes for a Single-Ended System 182.1.4 Current Profiles in a Push-Pull Driver 18Push-Pull Driver with CTT 19Push-Pull Driver with Power Termination 222.1.5 Noise for Push-Pull Driver 252.2 Differential Drivers and Receivers 262.2.1 Termination Schemes for Differential System 282.2.2 Current Profiles in Half Differential Driver 302.2.3 Noise for Half Differential Driver 322.3 Prior Stages of I/O Interface 34References 35Chapter 3 Electromagnetic Effects 373.1 Electromagnetic Effects on Signal/Power Integrity 373.2 Electromagnetic Theory 393.2.1 Maxwell's Equations 403.3 Transmission Line Theory 463.4 Interconnection Network Parameters: Z,Y,S and ABCD 553.4.1 Impedance Matrix [Z] 563.4.2 Admittance Matrix [Y] 573.4.3 The Scattering Matrix [S] 573.4.4 The Scattering Matrix [S] with Arbitrary Loads 593.4.5 Relation Between Scattering Matrix [S] and Y/Z/ABCD Matrix 613.5 LTI System 643.5.1 Reciprocal Network 643.5.2 Parameter Conversion Singularity 643.5.3 Stability 653.5.4 Passivity 653.5.5 Causality 67References 67Chapter 4 System Interconnects 694.1 PCB Technology 694.2 Package Types 704.3 Power Distribution Network 734.3.1 PCB PDN 73Power Supply 74DC/DC Converter 75PCB Capacitors 76PCB Power/Ground Planes 81Impact of Vias 87Stitching Domains Together 904.3.2 Package Power Distribution Network 924.3.3 On-Chip Power Network 93Intentional Capacitors 94Unintentional Capacitors 964.4 Signal Distribution Network 974.4.1 PCB/ Package Physical Signal Routing 97Microstrip Line 97Stripline 100Co-Planar Waveguide 101Coupled Lines 1024.4.2 Package Signal Distribution Network 1074.4.3 PCB/Package Material Properties 108Electrical Properties of Metal 108Electrical Properties of Dielectrics 110Frequency-Dependent Parameters of Microstrip Line 1114.4.4 On-Chip Signal Network 1124.5 Interaction Between Interconnect Systems 1154.5.1 Reference, Ground, and Return Paths 1164.5.2 Referencing: Single-Ended and Differential Signaling 1164.5.3 Power to Signal Coupling 1184.6 Modeling Tools for the PDN and Signal Networks 119References 122Chapter 5 Frequency Domain Analysis 1275.1 Signal Spectrum 1285.1.1 Fourier Transform Interpretation 1325.1.2 Important Properties of the Fourier Transform 134Interpreting and Using Frequency Domain Representations of Waveforms 134Key Properties of Fourier Transforms (of Interest in SI) 134Fourier Transform Examples and Interpretation 135Trapezoidal Pulse Fourier Transform Tool 1385.1.3 FFT of Power Noise 1415.1.4 Convolution and Filtering 1425.2 Signal and Power Integrity Applications 1435.2.1 S-Parameters with Global and Local Ground 1455.3 Power Distribution Network Design in Frequency Domain 1475.3.1 Impedance Response Z11 1485.3.2 Impedance Targets for I/O Interface 150Single-Ended Driver 151Differential Driver 152Prior Stages 1525.3.3 PDN Design Example 153Package and PCB PDN 154PDN Co-Design: PCB, Package and Chip 1555.3.4 On-Chip Power Delivery: Modeling and Characterization 158Test Vehicle for On-Chip PDN 1592D TLM Empirical On-Chip PD Modeling Method 161On-Chip Capacitor Model Extraction 162Modeling and Correlation for On-Chip PDN of the I/O Interface 163EM Modeling of On-Chip PDN 1655.3.5 Insertion Loss and Voltage Transfer Function 1665.3.6 SSO in Frequency Domain 1685.3.7 Power-to-Signal Coupling 1705.4 Signal Network Design in Frequency Domain 1715.4.1 Frequency Domain Optimization 1725.4.2 Simulation and Correlation of Signal Network 1745.4.3 Case Study: Crosstalk Amplification by Resonance 175Model Correlation 177Self-Impedance and Insertion Loss for the Entire Channel 180Voltage Transfer Function for the Victim Bit 181Far-End Crosstalk 182Self-Impedance and Transfer Impedance with Different Enablers 1835.4.4 Differential Signaling in Frequency Domain 184References 190Chapter 6 Time Domain Analysis 1936.1 Time Domain Modeling and Simulation 1936.1.1 Transient Simulations 1956.1.2 Buffer Modeling 196IBIS and VCR Models 1966.2 Simulation for Optimization 1986.2.1 Power Delivery Time Domain Specification 1986.2.2 Controllable Design Variables for Optimization 200Geometry and Material 201Passive Components on PCB and Package 203On-Chip Design Variables 2036.3 PDN Noise Simulations 2046.3.1 VR Tolerance and IR Drop 2046.3.2 AC Noise Analysis 207Supply Droop and Resonance 2076.3.3 Internal Circuits 2096.3.4 Final Stage Circuits 2106.3.5 Single-Ended Systems 212Correlation with Measurements 214Noise Measurements at the Receiver 2156.3.6 Differential Systems 2176.3.7 Logic Stage 2206.4 Jitter Impact for Time Domain Analysis 2216.4.1 Jitter Impact Due to PDN Noise 2226.4.2 Jitter Due to the SSO 223Single-Ended System 223Differential System 228References 231Chapter 7 Signal/Power Integrity Interactions 2337.1 Background 2347.2 Root Cause Analysis 2367.3 SSO Coupling Mechanism 2387.4 Case Study I: DDR2 800 Control Signal 2417.4.1 Noise Source 2437.4.2 Coupling Mechanism 2447.4.3 Resonant Structure on Control Networks 2457.4.4 Proposed Solutions 2477.5 Case Study II: DDR2 667 Vref Bus 2487.5.1 Noise Source 2497.5.2 Coupling Mechanism 2497.5.3 Resonance Structure 2507.5.4 Proposed Solutions 2527.6 Referencing/Stitching/Decoupling Effects--Single-Ended Interface 2587.7 Stitching Effects--Differential Interface 2637.7.1 VNA Measurement Results 2717.7.2 Modeling and Measurement Correlations 2737.7.3 System-Level Impact Evaluation 2747.8 EMI Trade-Off 2767.8.1 Power Islands Radiation 276References 282Chapter 8 Signal/Power Integrity Co-Analysis 2858.1 Identifying Controllable Parameters 2868.2 SI-PI Modeling and Simulation 2888.2.1 Modeling SI-PI Compatible Buffers 2888.2.2 Modeling On-Chip Passive Components 2908.2.3 Modeling Off-Chip Passive Components 2918.2.4 Model Check and Integration 2918.2.5 Construction of SI-PI Co-Simulation 2928.2.6 PDN Resonance Excitation of Driver Bit Pattern 2928.2.7 Worst-Case Eye 2948.2.8 Running SI-PI Co-Simulation 296ISI and Minimal ISI 297ISI and SSO 298ISI and Crosstalk 299ISI, SSO, and Crosstalk 2998.3 SI-PI Co-Analysis 3018.3.1 Time Domain Analysis 301Optimization Using Sweep Parameters and Noise Decomposition 302Simple Comparison of Eye 3058.3.2 Eye Diagram Analysis 3088.3.3 Linear Interaction Indicator 309Single-Ended Signaling SI-PI Performance and Linearity 315Differential Signaling SI-PI Performance and Linearity 317SI-PI Linear Interaction Indicator 3198.4 SI-PI Co-Simulation and Co-Analysis Flow: Summary 321References 322Chapter 9 Measurement Techniques 3259.1 Frequency Domain Characterization 3259.1.1 Vector Network Analyzer (VNA) 3269.1.2 Smith Chart 3279.1.3 Low-Impedance VNA Measurement for Power Delivery Network 3299.1.4 On-Chip Characterization 335On-Chip Interconnect 2D Modeling and Correlation 338On-Chip Interconnection Line Performance Versus Different Structures 345On-Chip PDN Characterization 3499.1.5 Pad Capacitance Characterization 350Lower- and Upper-Frequency Limit 350De-Embedding Method 3519.1.6 Power Delivery-to-Signal Coupling Measurement 3539.2 Equivalent Circuit Model Extraction 3559.2.1 Need for an Equivalent Circuit Model 355Validation Purpose 355Simulation Purpose 3569.2.2 Extraction Methodology 357Numerical Error 3589.2.3 Extraction Examples 358Receiver Model for SI 358PDN Model 360Topology Identification 3609.2.4 Extension to Multiport Measurement 3619.3 Time Domain Characterization 3619.3.1 Time Domain Reflectometry (TDR) 361Development of 9ps TDR Measurement Setup 363Package Validation Using TDR 365Differential TDR and TDT 3719.3.2 PDN Noise Measurement 3729.3.3 SSO Coupling Measurement in Time Domain 3769.3.4 Jitter Measurement 379References 380Index 383
