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New Techniques and Tools for Ensuring On-Chip Power Integrity-Down to Nanoscale As chips continue to scale, power integrity issues are introducing unexpected project complexity and cost. In this book, two leading industry innovators thoroughly discuss the power integrity challenges that engineers face in designing at nanoscale levels, introduce new analysis and management techniques for addressing these issues, and provide breakthrough tools for hands-on problem solving.Raj Nair and Dr. Donald Bennett first provide a complete foundational understanding of power integrity, including ULSI issues, practical aspects of power delivery, and the benefits of a total power integrity approach to optimizing chip physical designs. They introduce advanced power distribution network modeling, design, and analysis techniques that highlight abstraction and physics-based analysis, while also incorporating traditional circuit- and field-solver based approaches. They also present advanced techniques for floorplanning and power integrity management, and help designers anticipate emerging challenges associated with increased integration. Anasim RLCSim.exe, a new tool for power integrity aware floorplanning, is downloadable for free at anasim.com/category/software.The authorsSystematically explore power integrity implications, analysis, and management for integrated circuitsPresent practical examples and industry best practices for a broad spectrum of chip design applicationsDiscuss distributed and high-bandwidth voltage regulation, differential power path design, and the significance of on-chip inductance to power integrityReview both traditional and advanced modeling techniques for integrated circuit power integrity analysis, and introduce continuum modelingExplore chip, package, and board interactions for power integrity and EMI, and bring together industry best practices and examplesIntroduce advanced concepts for power integrity management, including non-linear capacitance devices, impedance modulation, and active noise regulationPower Integrity Analysis and Management for Integrated Circuits' coverage of both fundamentals and advanced techniques will make this book indispensable to all engineers responsible for signal integrity, power integrity, hardware, or system design-especially those working at the nanoscale level.
Contents
Preface xv Acknowledgments xxiAbout the Authors xxiiiContributors xxvChapter 1: Power, Delivering Power, and Power Integrity 11.1 Electromotive Force (emf) 11.2 Electrical Power 51.3 Power Delivery 81.4 Power Integrity (PI) 131.5 Exercises 17References 18Chapter 2: Ultra-Large-Scale Integration and Power Challenges 192.1 Exponential Integration and Semiconductor Scaling 202.2 Power and Energy Consumption 272.3 Power, Heat, and Power Integrity Challenges 392.4 Exercises 50References 51Chapter 3: IC Power Integrity and Optimal Power Delivery 533.1 Power Transfer and Efficiency 533.2 Optimal IC Power Delivery: On-Chip Inductance and Grid Design 813.3 Power Grid Cost Factor Trade-off Analysis and Design 993.4 Exercises 106References 107Chapter 4: Early Power Integrity Analysis and Abstraction 1114.1 Process, Voltage, and Temperature: Design Verification Space 1124.2 Back-End and Front-End PI Analysis 1154.3 Simulation Environment for Models of High Abstraction Levels 1264.4 Abstraction and PI Analysis Examples 1294.5 Summary and Enhancements 1354.6 Exercises 136References 138Chapter 5: Power Integrity Analysis and EMI/EMC 1415.1 Introduction 1415.2 Analysis of Noise Generation and Propagation through a Power Distribution Network 1435.3 Modeling Decoupling Capacitors for Noise Mitigation in PDNs 1505.4 Current Design Methodology for Power Delivery Networks 1545.5 Modeling Methodologies 1595.6 Numerical Methods 1695.7 Power and Signal Delivery Analysis Tools and Limitations 1765.8 Power Integrity-Aware Electromagnetic Interference Analysis 1885.9 Strengths and Limitations of Existing Early EMI methodologies 1975.10 Early Power Integrity-Aware EMI Modeling and Analysis Flow 1985.11 SI, PI, and EMI Summary 2155.12 Exercises 216References 216Chapter 6: Power Distribution Modeling and Integrity Analysis 2216.1 Introduction 2216.2 Modeling of a Power Distribution Grid 2246.3 Numerical Analysis of Power Distribution Model 2296.4 Differential and Common-Mode Noise 2306.5 Verification and Error Analysis 2336.6 Modeling of On-Chip Bus Switching Current 2396.7 Verification of the Bus Model 2456.8 Bus Skewing to Reduce Power Distribution Noise 2486.9 Case Study: Reduction of Power Distribution Noise 2506.10 Exercises 2526.11 Appendix: Coefficients for Equation (6-37) 253References 255Chapter 7: Effective Current Density and Continuum Models 2597.1 Circuit and Model Simplification 2597.2 Definition of Effective Current Density 2607.3 Effective Current Density and Virtual Currents 2637.4 Symmetry in Networks Containing Conductors, Insulators, and Other Components 2637.5 A Continuum Model Using ECD 2647.6 Practical Application of a Continuum-Based Simulator to IC Floorplanning 2737.7 Continuum Models Compared to SPICE Models 2807.8 Model Enhancement for Nanoscale CMOS Integrated Circuits 2847.9 Exercises 285References 286Chapter 8: Power Integrity-Aware Chip Floorplanning and Design 2878.1 Design for Power Integrity: Nanometer Era Considerations 2878.2 Design for Power Integrity: Techniques 2918.3 Power Management and Power Integrity 300References 314Chapter 9: Power Integrity Management in Integrated Circuits and Systems 3179.1 Chip-Level PI Management 3189.2 System- and Package-Level PI Management 3319.3 Exercises 341References 343Additional Reading 346Chapter 10: Integration Technologies, Trends, and Challenges 34710.1 Chip-Level Integration 34810.2 Package-Level Integration 35210.3 Integration Trend for Power Integrity Management Components 366References 367Additional Reading 369Appendix A: ECD Continuum Model Derivation 371Appendix B: Derivation of the Helmholtz Equation for Planar Circuits 383Index 385
