Resource Efficient LDPC Decoders : From Algorithms to Hardware Architectures

Chandrasetty, Vikram Arkalgud/ Aziz, Syed Mahfuzul

Academic Press Inc（2017/12発売）

• 製本 Paperback:紙装版/ペーパーバック版／ページ数 190 p.
• 言語 ENG
• 商品コード 9780128112557
• DDC分類 621.382

Full Description

This book takes a practical hands-on approach to developing low complexity algorithms and transforming them into working hardware. It follows a complete design approach - from algorithms to hardware architectures - and addresses some of the challenges associated with their design, providing insight into implementing innovative architectures based on low complexity algorithms.
The reader will learn:



Modern techniques to design, model and analyze low complexity LDPC algorithms as well as their hardware implementation
How to reduce computational complexity and power consumption using computer aided design techniques
All aspects of the design spectrum from algorithms to hardware implementation and performance trade-offs

Contents

1. Introduction2. Overview of LDPC codes3. Structure and flexibility of LDPC codes4. LDPC decoding algorithms5. LDPC decoder architectures6. Hardware implementation of LDPC decoder7. LDPC decoders in multimedia communication8. Prospective LDPC applications

AppendixA : Sample C-Programs and MATLAB models for LDPC code construction and simulationB : Sample Verilog HDL codes for implementation of fully-parallel LDPC decoder architectureC : Sample Verilog HDL codes for implementation of partially-parallel LDPC decoder architecture