Designer's Guide to Vhdl (2 PAP/CDR)

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Designer's Guide to Vhdl (2 PAP/CDR)

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  • 製本 Paperback:紙装版/ペーパーバック版/ページ数 784 p.
  • 言語 ENG
  • 商品コード 9781558606746
  • DDC分類 005

Full Description

Since the publication of the first edition of The Designer's Guide to VHDL in 1996, digital electronic systems have increased exponentially in their complexity, product lifetimes have dramatically shrunk, and reliability requirements have shot through the roof. As a result more and more designers have turned to VHDL to help them dramatically improve productivity as well as the quality of their designs.VHDL, the IEEE standard hardware description language for describing digital electronic systems, allows engineers to describe the structure and specify the function of a digital system as well as simulate and test it before manufacturing. In addition, designers use VHDL to synthesize a more detailed structure of the design, freeing them to concentrate on more strategic design decisions and reduce time to market. Adopted by designers around the world, the VHDL family of standards have recently been revised to address a range of issues, including portability across synthesis tools.This best-selling comprehensive tutorial for the language and authoritative reference on its use in hardware design at all levels--from system to gates--has been revised to reflect the new IEEE standard, VHDL-2001. Peter Ashenden, a member of the IEEE VHDL standards committee, presents the entire description language and builds a modeling methodology based on successful software engineering techniques. Reviewers on have consistently rated the first edition with five stars. This second edition updates the first, retaining the authors unique ability to teach this complex subject to a broad audience of students and practicing professionals.


1 Fundamental Concepts2 Scalar Data Types and Operations3 Sequential Statements4 Composite Data Types and Operations5 Basic Modeling Constructs6 Case Study: A Pipelined Multiplier Accumulator7 Subprograms8 Packages and Use Clauses9 Aliases10 Case Study: A Bit-Vector Arithmetic Package11 Resolved Signals12 Generic Constants13 Components and Configurations14 Generate Statements15 Case Study: The DLX Computer System16 Guards and Blocks17 Access Types and Abstract Data Types18 Files and Input/Output19 Case Study: Queuing Networks20 Attributes and Groups21 Miscellaneous TopicsA SynthesisB The Predefined Package StandardC IEEE Standard PackagesD Related StandardsE VHDL SyntaxF DifferencesG Answers to ExercisesReferencesIndex