エリア配列相互連結ハンドブック<br>Area Array Interconnection Handbook

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エリア配列相互連結ハンドブック
Area Array Interconnection Handbook

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  • 製本 Hardcover:ハードカバー版/ページ数 1188 p.
  • 言語 ENG
  • 商品コード 9780792379195
  • DDC分類 621.3815

Full Description


This handbook provides a comprehensive treatment of area-array interconnections for both chips and microelectronic packages in terms of optimizing densification, functionality and reliability. It provides comparisons with alternative and competing technologies, clearly defining cost versus benefit tradeoffs and strategies. Process details are defined in the order of their typical manufacturing sequence, indicating tooling requirements and potential yield detractors. In addition, the handbook has individual chapters devoted to supporting disciplines that play a key role in satisfying the requirements of microelectronic package applications: efficient thermal-dissipation techniques, metallurgical and mechanical characteristics of interconnections and electrical design strategies. Area-array technology at both die and chip carrier levels offers the best opportunity of satisfying the demanding performance requirements that users at all levels of the product spectrum have come to expect.This handbook fully describes the "how and why" of the inherent elements of area-array technology that give rise to enhanced electrical and thermal dissipation capabilities, and densification to accommodate demanding design requirements, while at the same time accommodating size and cost reductions to enhance comfort and portability.

Table of Contents

Foreword                                           lxi
Preface lxiii
Editor Biographies lxvii
History of Flip Chip and Area Array Technology 1 (36)
Introduction 1 (1)
Early Electronics 1 (1)
Solid Logic Technology---The Birth of Flip 2 (5)
Chip Packaging
Pre-SLT Packaging 2 (2)
SLT Transistor Design 4 (1)
Die-Level Hermeticity and I/O Bumps 4 (1)
Flip Chip Non-Hermetic Packaging 5 (1)
Hybrid Integrated Circuit Technology 6 (1)
Early Ball-Connection Development 7 (3)
Gold Ball Terminals 7 (1)
Wettable Terminal Pads 7 (1)
Ball Collapse 7 (1)
Collapse solutions 8 (1)
Other terminal changes 8 (2)
C-4 Flip Chip Development 10 (2)
Thick-Film Electrode Problem with C4 10 (1)
Other Chip Changes in Integrated Circuits 10 (1)
Self-Alignment in C4 11 (1)
Thermal Cycle Solder-Joint Fatigue Life 12 (1)
Elongated bumps and fatigue life extension 12 (1)
Beginning of Area Array Pads on Chips 12 (5)
Protect Diodes 12 (1)
I/O Over Active Area 12 (1)
Substrate Thin-Film Metallization 12 (3)
Multilevel Thin-Film Substrate Wiring 15 (1)
Multilayer Ceramic Modules 15 (2)
Redistribution Layers 17 (1)
Multilayer Chip Writing 17 (1)
Peripheral to Area Array Shift 17 (1)
Alternative Interconnection Techniques 17 (4)
Beam Leads 17 (1)
Tape Automated Bonding 18 (1)
Wire Bonding 19 (2)
Peripheral vs Area Array Chip Wiring 21 (2)
Peripheral Limitations 21 (1)
I/O Requirements 22 (1)
Peripheral vs Area Array Efficiency 22 (1)
Packaging Technology 23 (8)
Transfer Molded Plastic Packages and 23 (1)
Surface Mount Assembly
Surface mount vs pin-in-hole assembly 23 (1)
Area Array Packaging 24 (1)
Ceramic Multichip Modules 24 (1)
High-performance capabilities 24 (1)
CTE-matching ceramic 25 (1)
State-of-the-art server packaging 26 (1)
Direct Chip Attach on Organics 26 (1)
Flip chip underfill materials 26 (1)
Commodity market impact 27 (1)
Plastic ball grid array package 27 (1)
Chip scale packages vs DCA 28 (3)
The Future Issues with Area Array 31 (6)
Widespread Availability of Low Cost, Good 31 (1)
Flip Chips
Reliability Requirements Appropriate for 31 (1)
the Application
The No-Pb Quandry for Electronic Packaging 31 (1)
Ceramic vs Organic Packaging 32 (1)
References 32 (5)
Part I Chip-Level Technology 37 (512)
Wafer Bumping 39 (78)
Introduction 39 (6)
IBM SLT and C4 Efforts 40 (1)
General Motors' Early Flip Chip 40 (1)
Inexpensive Plastic Packages 40 (1)
Growing Niche for Flip Chip 40 (1)
Electroplated C4 Evolution 40 (3)
SLC and DCA 43 (1)
The Interconnect Paradigm Shift 43 (1)
MCNC/Unitive Electroplated C4 43 (1)
Delphi-Delco/Flip Chip Technologies C4 44 (1)
TU Berlin/Fraunhofer/Pac Tech Bumping 44 (1)
MicroFab Solder Jet Bumping 44 (1)
Non-solder Adhesive Bumping 44 (1)
Recent Developments 44 (1)
Evaporative Bumping 45 (11)
IBM Copper Ball Solderable Terminal 45 (1)
Solder Pre-placement Choices 45 (1)
Solder Evaporation 45 (1)
BLM Evaporation 46 (1)
Sputter Cleaning 47 (1)
Wafer contamination problem 47 (1)
Ex situ sputter cleaning 47 (1)
In situ sputter cleaning 48 (1)
Rf sputter cleaning 48 (1)
Cr-Cu-Au/Solder Evaporation and Reflow 48 (1)
Chromium deposition 48 (1)
Chromium---copper codeposition or 48 (1)
``Phasing''
Solution-assisted spalling 48 (1)
Copper deposition 49 (1)
Au deposition 49 (1)
Solder deposition 49 (2)
Cu balling of SLT wafers 51 (1)
Reflowing solder at the wafer level 51 (1)
Extendibility to Larger Wafers 52 (1)
Modern Evaporation Tooling 52 (2)
Variations on the Theme 54 (1)
Evaporation through a polymer mask 54 (1)
Hitachi sputtered CrCuAu UBM 54 (1)
Tin-cap C4 54 (2)
Motorola E3 56 (1)
Electrodeposition of Solder Bumps 56 (10)
Introduction 56 (1)
Overview 56 (1)
History of Electrodeposited Solder Bumps 56 (1)
Philips ``IC on tape'' 56 (1)
Hitachi electroplate 57 (1)
APTOS copper stud 57 (1)
Unitive electronics' intermetallic etch 58 (1)
mask
VTT electronics' patterned 58 (1)
barrier---blanket seed process
AT&T resist-less 58 (1)
IBM's electrodeposited C4 59 (1)
AMP's silicon waferboard technology (SWT) 59 (1)
Process Flow Options 59 (1)
Discrete seed, copper plate, solder plate 60 (1)
Discrete seed, nickel plate, solder plate 61 (2)
Patterned barrier, blanket seed, solder 63 (1)
plate
Phased seed, solder plate 63 (1)
Issues in Electrodeposition of Solder 63 (1)
Bumps
Seed layer conductivity 63 (1)
Seed layer oxidation 64 (1)
Seed layer nucleation 64 (1)
Seed layer etching 64 (1)
Photoresist thickness 64 (1)
Photoresist patterning 64 (1)
Photoresist development 64 (1)
Electrochemical kinetics 64 (1)
Hydrogen overpotential 65 (1)
Alloy control 65 (1)
Deposition rate 65 (1)
Deposition uniformity 66 (1)
Bath control 66 (1)
Conclusion 66 (1)
Flex-on-cap Bumping Technology 66 (10)
Introduction 66 (1)
Solder Paste Bumping Technology 66 (1)
In situ wafer clean 66 (1)
UBM deposition 66 (1)
UBM patterning 67 (1)
Solder paste deposition 67 (1)
Production bump pitch roadmap 67 (1)
Bump mechanical specifications 67 (1)
Bump design rules 67 (1)
Repassivation 68 (1)
Bump height distribution 68 (1)
Bump Structure---UBM 68 (1)
Characteristics and requirements of UBM 68 (1)
Al/NiV/Cu UBM design 68 (4)
UBM compatibility with probed wafers 72 (1)
Bump Structure---Solder 72 (1)
Solder alloy control requirements 72 (1)
63Sn/Pb solder alloy 72 (1)
Low alpha particle solder 73 (1)
10Sn/Pb solder alloy 73 (1)
Lead-free solder alloys 73 (3)
Conclusions 76 (1)
Low-Cost Bumping Technology Based on 76 (12)
Electroless Ni and Solder Paste
Introduction 76 (1)
Electroless plating and maskless process 76 (1)
advantages
Electroless Ni/Au Under Bump 77 (2)
Metallization (UBM)
Electroless Ni/Au bumping---the process 79 (1)
steps
Electroless Ni/Au 79 (1)
bumping---characteristics
Electroless Ni/Au bumping---wafer design 80 (1)
rules
Solder Bumping Technology 81 (1)
Wafer level solder printing 81 (2)
Lead-free solder printing 83 (1)
Solder bumping for repair using single 83 (1)
point solder ball placement
Laser scan reflow balling 84 (2)
Bumping for 300 mm Wafers 86 (1)
Conclusions 86 (2)
Solder Jet Technology for Wafer Bumping 88 (5)
Introduction 88 (1)
Background of Ink-Jet Technology 88 (1)
Printhead 89 (1)
Drop Size Modulation 89 (1)
Print-on-the-Fly 90 (1)
Test Vehicle Printing/Bump Metallurgy 90 (1)
High and No-Lead Solders 91 (1)
Bumping demonstration and assessment 92 (1)
Conclusions 92 (1)
Conductive Adhesive Joining and Bumping for 93 (24)
DCA Applications
Introduction 93 (1)
Bumping 94 (1)
Electroplating 94 (1)
Electroless nickel bumps 95 (1)
Stud wire bumping 95 (1)
Polymer bumps 95 (1)
Adhesives 95 (1)
Contact mechanisms in adhesive joints 96 (1)
Isotropic Conductive Adhesive 96 (1)
Metal content increases elastic modulus 97 (1)
Underfill 97 (1)
ICA on Rigid Substrates 97 (1)
Polymer bumps 97 (1)
Plated metal bumps 98 (1)
Citizen LCD 98 (1)
Philips COG 98 (1)
Stud Ball Bumping (SBB) Process 98 (1)
Matsushita ICA 98 (1)
Fujitsu microprocessor 99 (1)
Anisotropic Conductive Adhesive 99 (1)
ACA bonding parameters 100 (1)
Criteria for a good flip chip joint 100 (1)
Softening of PCB 100 (1)
Material properties of adhesives 100 (2)
Deformation of filler particles 102 (1)
Examples of ACA 102 (3)
Solder-filled ACAs 105 (1)
Smart-card application 106 (1)
Flip chip on rigid board application 107 (1)
Use of Conductive Particles 107 (1)
Sharp; ``Elastic'' 107 (1)
Seiko Epson 108 (1)
Mitsubishi 109 (1)
Non-conductive Adhesive 109 (1)
Matsushita NCA 110 (1)
General Reliability and Degradation 111 (1)
Mechanisms
Conclusions 111 (1)
Acknowledgments 111 (1)
References 112 (5)
Wafer-Level Test 117 (32)
Introduction 117 (1)
Introduction to Test 117 (1)
Introduction to Probes 118 (1)
Test Strategy 118 (4)
Prime Tenet 118 (1)
Approach 118 (1)
Hierarchical flow 119 (1)
Design for test 119 (1)
Adoption of area-array technology 119 (2)
Fault modeling 121 (1)
Structural testing using scan techniques 121 (1)
Test Types 122 (6)
In-Line Tests 123 (1)
Test sites 123 (1)
Kerf structures 123 (1)
Pad layout 123 (1)
Probe constraints 124 (1)
Wafer Final Test 124 (1)
Wafer test ordering 124 (1)
Multiple test cycles 124 (1)
Test objectives 125 (1)
Wafer Probing Test Considerations 126 (1)
Product/test type 126 (1)
Physical layout 126 (1)
Die pad metallization 126 (1)
Probe types 126 (1)
Singulated die test 127 (1)
Probe interface 127 (1)
Space transformer 127 (1)
Power supply distribution 127 (1)
Remote sensing 127 (1)
Contact verification 127 (1)
Maintainability considerations 128 (1)
Product Probers and Handlers 128 (5)
Wafer Prober 128 (1)
Overview 128 (1)
Integral subsystem 128 (1)
Basic functions 129 (1)
Materials Handler 129 (1)
Wafer diameter/thickness consideration 129 (1)
Handling single wafers 130 (1)
Wafer IDs 130 (1)
Typical process flow 130 (1)
Alignment 130 (1)
Sophisticated systems 130 (1)
Alignment processes 130 (2)
Probe mark inspection 132 (1)
Environment control 133 (1)
Z-Drive considerations 133 (1)
Probes for Semiconductor Devices 133 (14)
Background 133 (1)
Introduction 134 (1)
Fundamental Requirements 135 (1)
Peripheral Probe Materials 136 (1)
Peripheral Probes 136 (1)
Guidelines 136 (1)
Ceramic-blade and metal-blade types 136 (1)
Epoxy-ring type 137 (1)
Area Array Probe Types 137 (1)
Design fundamentals 138 (1)
Buckling beam probes construction 139 (1)
Area-Array Hybrid Buckling Beam Probes 139 (1)
Design fundamentals 139 (1)
Hybrid buckling beam probe construction 140 (1)
Footprint Transformer 141 (1)
Area Array Road Map and Specification 142 (3)
Probe Properties 145 (1)
Force/deflection characteristics 145 (1)
Contact resistance 146 (1)
Future Trends in Probes 147 (2)
Acknowledgments 147 (1)
References 148 (1)
Known Good Die (KGD) 149 (52)
Introduction 149 (3)
Mainframe Computers 150 (1)
Personal Computers 151 (1)
Consumer Products 152 (1)
Network Centric Solution Requirements 152 (23)
Key Considerations 152 (1)
Multichip module 152 (1)
Availability 152 (2)
Test and burn-in 154 (1)
Enhancement rate 154 (1)
Requirements by Market Segments 154 (2)
KGD Requirements 156 (1)
Reliability driver 156 (1)
Quality driver 156 (1)
Other issues 157 (1)
Combined Die and Carrier Considerations 157 (1)
Heating and coefficient of thermal 158 (1)
expansion (CTE) mismatch issues
Miniaturization 159 (7)
Performance vs I/O scheme 166 (1)
Semiconductor Evolution-Driven KGD and 167 (1)
Packaging Requirements
Enhancements 167 (1)
On-chip operating voltage and power 168 (6)
dissipation
Exceeding projections 174 (1)
Known Good Die Production 175 (8)
Effect of KGD on MCM Yield/Cost 175 (1)
Temporary Die Attach for Burn-in and 176 (1)
Speed-Sort
Industry examples 177 (1)
Wafer-Level Test and Burn-in 178 (1)
Wafer-level test and burn-in probes 178 (4)
Full wafer system challenges 182 (1)
KGD Industry Infrastructure 183 (8)
Industry Initiatives 183 (1)
Introduction 183 (1)
Low-cost KGD objectives 184 (1)
KGD Infrastructure Changes 185 (1)
Technologies for KGD Market Growth 185 (1)
KGD Product Applications 185 (1)
Computers 186 (3)
Set top box and digital consumer 189 (1)
Wired communications 189 (1)
Wireless communications 190 (1)
Storage components 190 (1)
KGD Suppliers 190 (1)
KGD---Beyond Linear Extrapolation 191 (3)
Stacked KGD in 3 Dimensional 191 (1)
Configurations
Cube vs memory card 192 (1)
Cube in an aerospace application 192 (2)
Future Potential Technological Innovation 194 (7)
Enabled by KGD
Acknowledgments 197 (1)
References 197 (4)
Wafer Finishing---Dicing, Picking, Shipping 201 (27)
Die Separation Technology 201 (9)
Wafer Separation Overview 201 (2)
Wafer Mounting 203 (1)
Dicing Tools 203 (1)
Rigidity 203 (1)
Power 204 (1)
Cooling 204 (1)
Dicing Blades 204 (2)
Factors Affecting Dicing Variable Choices 206 (1)
Topside edge chipping 206 (1)
Backside edge chipping 207 (1)
Dual Spindle Dicing 208 (1)
Summary 209 (1)
Chip Picking Technology 210 (7)
Introduction 210 (1)
Chip Picking Equipment Overview 211 (1)
Picking process 211 (2)
Picked chip disposition 213 (1)
Picking Process Variables 213 (1)
Dicing tape 213 (1)
Wafer expansion 214 (1)
Needle design and application 214 (1)
Vacuum hold-down design 214 (1)
Vacuum pick-up tips 214 (1)
Equipment/Process Control 215 (1)
Wafer identification 215 (1)
Product quality and capacity concerns 215 (1)
Die Sorting and Mapping 216 (1)
Packing, Shipping and Handling of Dice 217 (7)
Introduction 217 (1)
Chip Trays 218 (1)
Waffle packs 218 (1)
GEL-PAK® 219 (1)
Carrier Tapes 220 (1)
Tape types description 220 (1)
Punched and embossed tapes 221 (1)
Benefits of tape and reel 221 (1)
Electrically conductive tapes 221 (1)
Cover Tapes on Carrier Tapes 221 (1)
Punched carrier 221 (1)
Embossed carrier 221 (1)
Limitations of punched or embossed tape 222 (1)
with covers
Adhesive-Enhanced Carrier Tape 222 (1)
Tape construction 223 (1)
Advantages over punched or embossed tapes 223 (1)
Flip chip advantages 224 (1)
Limitation 224 (1)
Summary 224 (1)
Future Directions and Development 224 (4)
Evolutionary Changes 225 (1)
Major Deviations 225 (1)
Acknowledgments 226 (1)
References 226 (1)
Additional Suggested References 227 (1)
Ceramic Chip Carriers 228 (40)
Introduction 228 (1)
Market and System Requirements 228 (6)
High Performance 232 (1)
Cost Performance 233 (1)
Commodity 233 (1)
Hand Held and Communication 233 (1)
Automotive 233 (1)
Memory 234 (1)
Materials and Product Types 234 (2)
Application Product Types 234 (1)
Materials and Properties 234 (1)
Alumina/mullite 235 (1)
High performance materials 235 (1)
High thermal conductivity 235 (1)
Fabrication Processes 236 (8)
Overview 236 (1)
Hybrid Thick Film Processing 237 (1)
Thick film processing 237 (1)
Photo-imageable and diffusion patterning 238 (1)
Pressed Ceramic Processing 238 (1)
Multi-Layer Ceramic 239 (1)
Dielectric raw materials processing 239 (1)
Punching 239 (1)
Thick film paste processing 240 (1)
Metallization 240 (1)
Stacking, lamination, and sizing 241 (1)
Sintering 242 (1)
Post sinter processing 242 (1)
Test and inspection 243 (1)
Feature sizes 243 (1)
Availability, Cost and Characteristics 243 (1)
Availability/characteristics 243 (1)
Cost 243 (1)
Ceramic Chip Carriers with Thin Films 244 (14)
Thin-Film Drivers/Applications 245 (1)
Electrical performance 245 (2)
I/O density 247 (1)
Material properties 247 (1)
Manufacturability 248 (1)
Thin-Film Structure 248 (1)
Basic structure 248 (1)
Complex structures 248 (2)
Materials 250 (1)
Conductors 250 (1)
Dielectrics 250 (1)
I/O metallization 251 (1)
Process Technologies 252 (1)
Dielectric coating processes 252 (1)
Dielectric via formation 253 (2)
Metal patterning 255 (2)
Multilayer Ceramic Factors 257 (1)
Ground Rules and Tradeoffs 257 (1)
Integral Passive Technology and Integrated 258 (2)
Solutions
Resistors 259 (1)
Capacitors 259 (1)
Other Applications 259 (1)
Chip Carrier Form Factors, Advantages and 260 (3)
Limitations
Die-to-Chip-Carrier Area-Array 260 (1)
Interconnections
Interconnection density 260 (1)
Interconnection reliability 261 (1)
Additional factors 261 (1)
Package-to-Board Area-Array 262 (1)
Interconnections
Ball grid array interconnections 262 (1)
Column grid array interconnections 262 (1)
Land grid array interconnections 262 (1)
Pin grid array interconnections 262 (1)
Ceramic vs. Laminate Carriers 262 (1)
Future Trends/Directions 263 (5)
Area Array Packages 263 (1)
Applications 264 (1)
Ceramic Chip Carriers 264 (1)
Thin Films 264 (1)
References 265 (3)
Laminate HDI Die Carriers 268 (47)
Introduction 268 (3)
What Is HDI 268 (1)
Advantages and Benefits 268 (1)
Benchmarks 269 (1)
Design/Cost/Performance Tradeoffs 269 (1)
Specifications and Standards 269 (2)
HDI Structures 271 (2)
Construction 271 (1)
Type I constructions: 1[C]0 or 1[C]1 271 (1)
Type II constructions: 1[C]0 or 1[C]1 271 (1)
Type III constructions: ≥ 2[C] ≥ 0 272 (1)
Type IV constructions: 1[P]0 or 1[P]1 or 272 (1)
> 2[P] > 0
Design Rules 272 (1)
Category A 273 (1)
Category B 273 (1)
Category C 273 (1)
Category D 273 (1)
Design 273 (5)
Design Tools 273 (1)
Required features of HDI CAD toolsets and 273 (1)
autorouters
Autorouters 273 (1)
Trade-Off Analysis 273 (4)
Total Wiring Requirements 277 (1)
Wiring demand vs. substrate capacity 277 (1)
Materials 278 (3)
HDI Material Requirements 278 (1)
Copper Clad Dielectrics 278 (1)
Coated copper foils 278 (1)
Non-woven, non-glass reinforced laminate 279 (1)
Unclad Non-Reinforced Dielectric 280 (1)
Photoimageable dielectrics 280 (1)
Non-photoimageable, non-reinforced 281 (1)
dielectric
Build Up Technologies 281 (4)
Via Formation Processes 281 (1)
Mechanical drilling 281 (1)
Photo-sensitive dielectrics 282 (1)
Laser drilling 283 (1)
Plasma etching 284 (1)
Insulation displacement 284 (1)
Photo-Defined Via Technologies 285 (6)
Surface Laminar Circuit™ Technology 285 (1)
Background 285 (1)
Examples of SLC applications 286 (1)
SLC technology process 286 (1)
Design rules 286 (2)
SLC technology reliability 288 (1)
IPN Polymer Build-Up Structure System 288 (2)
(IBSS)
Design rules 290 (1)
Carrier Formed Circuits 290 (1)
Manufacturing process 290 (1)
Laser Generated Vias 291 (6)
Laser Formed Blind/Through Vias 291 (1)
Structure 292 (1)
Manufacturing process 292 (3)
Laser Drilled Flex (ViaThin) 295 (1)
Structure 295 (1)
Application examples 295 (1)
Manufacturing process 296 (1)
Design rules 296 (1)
High Density Interconnect (GE-HDI) 296 (1)
Chemical/Metallurgical-Bonded Via in PWB 297 (6)
Technologies
Sequential Bonded Laminate (ALIVH) 297 (1)
Structure 297 (1)
Application example 298 (1)
Manufacturing process 298 (1)
Microfilled Via Technology 299 (3)
Structure 302 (1)
CTS and Ormet Conductive Paste Adhesive 302 (1)
Co-lamination (ViaPly®) 302 (1)
Application example 302 (1)
Structure 302 (1)
Manufacturing process 303 (1)
Unique materials 303 (1)
Plasma Etched Vias 303 (5)
DYCOstrate® 304 (1)
Structure 304 (1)
Application examples 304 (1)
Manufacturing process 305 (1)
Design rules 305 (1)
Plasma micro-milling 305 (1)
Plasma Etched Redistribution Layers (PERL) 306 (1)
Structure 307 (1)
Application examples 307 (1)
Manufacturing process 307 (1)
Reliability information 307 (1)
Insulation Displacement Technology 308 (1)
Buried Bump Interconnect (BbiT) 308 (1)
Structure 308 (1)
Manufacturing process 308 (1)
Summary 309 (1)
Future Enhancements 310 (5)
References 311 (4)
Flip-Chip Die Attach Technology 315 (35)
Introduction 315 (1)
Die Attachment Methods 315 (1)
Wire bonding 315 (1)
Tape automated bonding (TAB) 315 (1)
Flip Chip Motivation/Attributes 315 (1)
Solder Joint Requirements 316 (1)
Bulk solder 316 (1)
Attachment 316 (1)
Complex Structures 316 (1)
Functional Requirements 316 (1)
Signal Interconnects 316 (1)
Power Distribution 317 (1)
Mechanical Protection 317 (1)
Heat Dissipation 317 (1)
Flip-Chip Terminals 317 (6)
Bond Pad (Under Bump Metallurgy) 317 (1)
Solder Deposition Techniques 318 (1)
Evaporated solder 318 (1)
Plated solder 318 (1)
Screened solder 319 (1)
Wire bond to flip-chip terminal conversion 320 (1)
Factors to consider 320 (1)
Pre-Attachment Reflows 320 (1)
Homogenization 320 (1)
Shape restoration 321 (1)
Metallurgical effects 321 (1)
Reestablish hermiticity 321 (1)
Low-Melt Solder Bumps 322 (1)
The need 322 (1)
Single-metal system 322 (1)
Dual-metal system 322 (1)
Chip Storage 323 (1)
Chip-Carrier Pads 323 (3)
Nature of Microsocket Pads 323 (1)
Planarity requirements 323 (1)
Metallization protection 323 (1)
Low-melt pre-tin 323 (1)
Laminate Solder Deposition for Single and 324 (1)
Dual-Metal Flip Chips
Paste screening 324 (1)
Plating 324 (1)
Solder jetting 324 (1)
Solder injection 325 (1)
Chip Carrier Pre-clean 325 (1)
Materials/methods 325 (1)
Organic residues 325 (1)
Failure to clean 325 (1)
Ambient Control Requirement 325 (1)
Flux 326 (5)
Purpose/Function 326 (1)
Flux Types 326 (1)
Rosin-based fluxes 326 (1)
Flux Mechanisms 327 (1)
Remove adsorbed gases/tarnish 327 (1)
Egg-shell concept 328 (1)
Complexing 328 (1)
Mechanism summary 328 (1)
Flux Application 328 (1)
Methods 328 (1)
Quantity 328 (1)
Elevated Temperature Effects 329 (1)
Loss of stability/activity 329 (1)
Charred residues 329 (1)
Alternatives 329 (1)
Synthetic fluxes 330 (1)
Gaseous fluxes 330 (1)
Plasma processes 331 (1)
Die/Pick-up/Place 331 (2)
Inspection of Bumped Die 331 (1)
Pickup and Place Tool Features 332 (1)
Planarity/alignment 332 (1)
Vision system 332 (1)
Placement speed 332 (1)
Tool flexibility 333 (1)
Place Condition 333 (1)
Placement force 333 (1)
Reflow 333 (4)
Requirements 334 (1)
Wettability Testing 334 (1)
Furnaces Types 334 (1)
Furnace Atmosphere 335 (1)
Thermal Profiles 335 (1)
Heat-up rate 335 (1)
Plateau 335 (1)
Peak temperature/dwell time 336 (1)
Cooling down 336 (1)
Furnace exit temperature 336 (1)
Heating Individual Chips 336 (1)
Temperature Profiles 336 (1)
Quality control monitors 337 (1)
Post-Reflow Clean 337 (2)
Purpose 337 (1)
Method 337 (1)
Criteria 337 (1)
Nature of Contaminants 337 (1)
Standard Practice 337 (1)
Environmental Concerns 338 (1)
Alternative Cleaning Technologies 338 (1)
Non-CFC solvents 339 (1)
Aqueous cleaning 339 (1)
No-clean technology 339 (1)
Interconnection Characterization 339 (5)
Solder Joint Metallurgy 339 (1)
Solder-to-die pad structures 339 (1)
Solder-to-chip carrier structures 340 (1)
Bulk solder 340 (1)
Role of solder joint constitutents 340 (1)
Characterization/Diagnostic Techniques 340 (1)
Sources of Defects 341 (1)
Flip-Chip Interconnection Defects 341 (1)
Improper wetting conditions 341 (1)
Voids in solder joints 342 (1)
Separations 343 (1)
UBM failure 344 (1)
Die-Level Defective Conditions 344 (1)
Punch through 344 (1)
Summary 344 (2)
Types of Solder Bumps 344 (1)
Flux 344 (1)
Furnaces 345 (1)
Furnace atmosphere 345 (1)
Profile 345 (1)
Post-Reflow Clean 345 (1)
Joint Metallurgy 345 (1)
Defective Conditions 346 (1)
Future Trends 346 (4)
Device I/O Counts/Density 346 (1)
Materials Technology 346 (1)
Direct Chip Attachment 346 (1)
Flux/Fluxless 347 (1)
Acknowledgments 347 (1)
References 347 (3)
Solder Bump Flip-Chip Replacement Technology 350 (21)
on Ceramic Carriers
Introduction 350 (1)
Reasons for Replacement 350 (1)
Method Priority 350 (1)
Quality/Repeatability 351 (1)
Enable Implementing Future Enhancements 351 (1)
Mechanical Methods of Chip Removal 351 (2)
Tensile Pull 351 (1)
Torque Removal 351 (1)
Limitations 352 (1)
Ultrasonic Removal 352 (1)
Transducers/coupling 353 (1)
Advantages/limitations 353 (1)
Localized Heating Chip Removal Methods 353 (5)
Universally-Heated Chip Carrier 354 (1)
Local Heating 354 (1)
Conduction methods 354 (1)
Convection methods 355 (1)
Radiation methods 355 (1)
Challenges 356 (1)
General Thermal Profile 357 (1)
Global Heating Chip Remove Methods 358 (2)
General Thermal Profile 358 (1)
Removal Methods 358 (1)
Spring/bimetallic 358 (1)
Vacuum removal 359 (1)
Residual Solder Uniformity 360 (1)
Broken Chip Removal 360 (1)
Site Dress 361 (6)
Why Site Dress 361 (1)
Mechanical Dress (Shave) 362 (1)
Molten Solder Dress Techniques 363 (1)
Hot gas 363 (1)
Solder wettable slug 364 (1)
Solder Decal Transfer 365 (1)
Construction 365 (1)
Utilization 365 (1)
Potential detractors 365 (1)
Selective Solder-Bump Removal and Replace 366 (1)
Rework Joint Characteristics/Integrity 367 (1)
Dimensional Characteristics 367 (1)
Interface Integrity 367 (1)
Reliability 368 (1)
Summary 368 (1)
Mechanical vs. Thermal Chip Removal 368 (1)
Methods
Site Dress 368 (1)
Local vs. Furnace Reflow Attachment 368 (1)
Reliability 368 (1)
Future Trends 369 (2)
Acknowledgments 369 (1)
References 369 (2)
Manufacturing Considerations and Tools for 371 (50)
Flip Chip Assembly
Introduction 371 (1)
Product Release 372 (1)
Flux Application 372 (2)
Application Methods/Tools 372 (1)
Manual application 372 (1)
Spray fluxing 372 (1)
Contact fluxing 372 (1)
Accessibility 373 (1)
Manufacturing Practice 373 (1)
Flux quantity and type 373 (1)
Selecting a dispense method 373 (1)
Preparation for Device Placement 374 (2)
Receiving/Storage 374 (1)
Component Identification 375 (1)
Part Introduction 376 (1)
Flip chips 376 (1)
Surface mount components 376 (1)
Chip carriers 376 (1)
Flip Chip Placement 376 (4)
Tooling 376 (1)
Placement accuracy 377 (1)
Manual chip-placement tools 377 (1)
Automated chip-placement tools 378 (1)
Placement Operation 378 (1)
Program input 378 (1)
Carrier location 378 (1)
Flip chip alignment and placement 378 (1)
Surface mount device (SMD) alignment and 379 (1)
placement
Solder paste dispense 379 (1)
Post-Placement Inspection 380 (1)
Flip Chip Attachment 380 (6)
Furnace Types/Heating Mechanisms 380 (1)
Electrical resistance 380 (1)
Infrared 381 (1)
Furnace Atmosphere Control 382 (1)
Monitors 382 (1)
Gas Flows and Cooling Methods 382 (1)
Manufacturing Considerations 382 (1)
Product mass 382 (1)
Fixture mass 383 (1)
Utilize a profile plateau 383 (1)
Raiative properties 383 (1)
Fixtures 384 (1)
Durability 384 (1)
Multiple process capability 384 (1)
Process Setup 384 (1)
Furnace monitors 384 (1)
Temperature measurement 385 (1)
Profile development 385 (1)
Process Verification and Control 385 (1)
Furnace monitors 385 (1)
Monitor frequency 386 (1)
Flux Cleaning 386 (3)
Flux Types 387 (1)
Overview 387 (1)
Rosin-based fluxes 387 (1)
Water-based fluxes 387 (1)
Process Impacts 387 (1)
Monitors 388 (1)
Cost Considerations 388 (1)
Cleaning Methods 388 (1)
Waste Disposal 389 (1)
Rework 389 (2)
Decision to Rework 389 (1)
Maintain Integrity 390 (1)
Communication and Documentation 390 (1)
Proximity 390 (1)
Warning monitors 390 (1)
Traceability 390 (1)
Temperature Hierarchy 390 (1)
Chip Underfill 391 (3)
Dispense 391 (1)
Normal dispense 391 (1)
Congested areas 391 (1)
Dispense pattern 392 (1)
Dispense volume 392 (1)
Cure 392 (1)
Hermetic vs Non-hermetic Modules 392 (1)
Dispense Equipment 393 (1)
Time/pressure systems 393 (1)
Positive displacement systems 393 (1)
Underfill dispense equipment 393 (1)
Internal Thermal Enhancements 394 (2)
Thermal Paste 394 (1)
Volume requirements 394 (1)
Voids 394 (1)
Lid attachment 395 (1)
Thermal Paste Dispense 395 (1)
Thermal paste characteristics 395 (1)
Dispense methods 395 (1)
Other Cooling Methods 395 (1)
Thermal contacts 395 (1)
Direct liquid cooling 395 (1)
Pistons 396 (1)
Module Encapsulation and Seals 396 (5)
Capless 397 (1)
Direct Lid Attach (DLA) 397 (1)
Bond line 397 (1)
Multiple chips 398 (1)
Lid tilt 398 (1)
Non-Hermetic 398 (1)
Standard caps/seals 398 (1)
Corner cap 399 (1)
Encapsulation/capping equipment 399 (1)
Curing equipment 399 (1)
Hermetic 400 (1)
Solder seals 400 (1)
Seam seals 401 (1)
Mechanical seals 401 (1)
Marking 401 (2)
Laser Marking 402 (1)
Inkjet 402 (1)
Offset Printing 403 (1)
Stamp Printing 403 (1)
Final Inspection 403 (1)
Manual Inspection 403 (1)
Automated Inspection 404 (1)
Advances 404 (1)
Equipment considerations 404 (1)
Limitations 404 (1)
Leak Testing 404 (1)
Bubble Leak 405 (1)
Helium Bomb 405 (1)
Helium Fill 405 (1)
Design for Manufacturability 405 (4)
Fixturing 405 (1)
Chip carrier shape and size 405 (1)
Chip carrier orientation locator 406 (1)
Module I/O 406 (1)
Marking 406 (1)
Device Placement and Join 407 (1)
Component spacing 407 (1)
Flip-chip array design 407 (1)
Die corner fiducials 407 (1)
Rework 407 (1)
Component spacing 407 (1)
Temperature hierarchies 408 (1)
Die Underfill 408 (1)
Excluded areas 408 (1)
Handling 409 (2)
Component Containers 409 (1)
Automation 409 (1)
Product Transportation 409 (1)
Component Handling 410 (1)
Flip chips 410 (1)
Surface mount devices 410 (1)
Pinned and no-lead components 410 (1)
Electrostatic Discharge (ESD) Protection 410 (1)
Triboelectricfication 410 (1)
Static discharge 411 (1)
Prevention 411 (1)
Parts Storage 411 (1)
Moisture Sensitive Components 411 (1)
Flip Chip Storage 412 (1)
Flip Chip Yields 412 (7)
General Yield Learning 412 (1)
Monitor yield detractors 412 (1)
Timely assessments 413 (1)
Process Requirement Relationship 414 (1)
Low-complexity example 414 (1)
High-complexity example 414 (1)
Rework Cost vs. Yield 415 (1)
Killer vs. Cosmetic Defects 415 (1)
Visual Inspections 416 (1)
Process Control Monitors 417 (1)
Flip chip process control monitors 417 (1)
Sector parameter controls 417 (1)
Assembly Yield Controls 418 (1)
Controllable factors 418 (1)
Defect isolation tools 418 (1)
Future Trends 419 (2)
Acknowledgments 419 (1)
References 419 (2)
Test and Burn-in Sockets 421 (31)
Introduction 421 (1)
Test vs Burn-in Requirements 421 (1)
Quality/Reliability 422 (1)
Socket Selection 422 (1)
Chapter Structure 422 (1)
Implications of Large Arrays 422 (4)
Reduced Pin Test 423 (1)
Power Consumption Effects on Supply 424 (1)
Inductance
Power supply inductance 424 (1)
Locating leaking capacitors 424 (1)
Socket and Device Interface Board 425 (1)
Verification
Verification methods 425 (1)
Contact failure 426 (1)
Electrical Performance 426 (4)
Correlation 426 (1)
Contact Resistance 427 (1)
Initial contact resistance 427 (1)
Long-term resistance 427 (1)
Impact of contact resistance 428 (1)
Contact Inductance 428 (1)
Self inductance 428 (1)
Effects/implications 429 (1)
Mutual inductance 429 (1)
Many contactors in parallel 429 (1)
Contact Capacitance 429 (1)
Microwave sockets 430 (1)
Socket Reliability/Failure Modes 430 (2)
Failure Categories 430 (1)
Accelerated Testing 430 (1)
Screen Testing 431 (1)
Burn-In Testing 431 (1)
Failure Due to Cyclic Stress Conditions 431 (1)
Fretting wear 432 (1)
Fatigue 432 (1)
Socket durability 432 (1)
Socket Qualification 432 (4)
Introduction 432 (1)
Manufacturers Qualification 432 (1)
Quality audits 433 (1)
Procedures/specifications 433 (2)
User Qualification 435 (1)
Cost trade offs 435 (1)
Requirements 435 (1)
Burn-in Sockets 436 (9)
Burn-in Socket Considerations 436 (1)
Types of Area Array Sockets 436 (1)
Force 436 (1)
Alignment 437 (1)
Tolerance example 438 (1)
Contact Type 438 (1)
Handling 439 (1)
Contamination 439 (1)
Burn-in Methodology Considerations 440 (1)
Area array dice/MCM challenges 440 (1)
Reduced pin count 441 (1)
MCM burn-in vs KGD 442 (1)
Thermal cycle stress 442 (1)
Burn-in Equipment Considerations 442 (1)
High power issues 443 (2)
Basic Socket Descriptions 445 (5)
Actuation Mechanisms 445 (1)
Latched-door type 445 (1)
Vertical displacement type 445 (1)
Open top type 445 (1)
Auto Handlers 446 (1)
Features/benefits 446 (1)
Temperature control 446 (1)
Typical Commercially-Available Contactor 446 (1)
Systems
Materials 446 (1)
Contactor configurations 447 (1)
Contactor force 448 (1)
Stiffeners 448 (1)
Temperature control 449 (1)
Monitoring power supply current 449 (1)
Future Module-Test Trends 450 (2)
Consumer Electronics 450 (1)
Data Processing Applications 450 (1)
General Trends 450 (1)
Acknowledgments 450 (1)
References 450 (2)
Underfill: The Enabling Technology for 452 (48)
Flip-Chip Packaging
Introduction 452 (3)
Fatigue-Life Enhancement 452 (1)
Technology Drivers 453 (1)
Reasons for Enhanced Reliability 453 (1)
Underfill as Enabler of Flip-Chip 454 (1)
Applications
Disadvantages 454 (1)
Flip Chip Underfill Applications 455 (3)
Usage Classifications 455 (1)
Form Factor 455 (1)
Application Examples 456 (1)
Automotive 456 (1)
Personal computers and workstations 456 (2)
Personal communications 458 (1)
Uncured Material Properties 458 (6)
Solids Content 459 (1)
Pre-Mixed vs. Unmixed 459 (1)
Shelf Life 459 (1)
Pot Life 460 (1)
Filler Particle Size 460 (1)
Filler Separation 461 (1)
Viscosity 461 (1)
Surface Tension 462 (1)
Cure 462 (1)
Color 463 (1)
Containers 463 (1)
Cured Material Properties 464 (4)
Coefficient of Thermal Expansion (CTE) 464 (1)
Effect of filler loading 464 (1)
Effect of temperature 464 (1)
Glass Transition Temperature (Tg) 465 (1)
Effect of Tg on underfill material 465 (1)
properties
Factors that affect Tg 465 (1)
Elastic Modulus 465 (1)
Tensile Strength 466 (1)
Electrical Properties 466 (1)
Moisture Resistance 466 (1)
Extractable Ion Content 467 (1)
Alpha-Particle Emission 467 (1)
Thermal Conductivity 468 (1)
Adhesion 468 (4)
Composition 469 (1)
Die Passivation Surfaces 469 (1)
Effect of passivation coating 469 (1)
Cleanliness of passivation 469 (1)
Plasma and silane treatments 470 (1)
Manipulating cure 470 (1)
Die Edges 470 (1)
Board/Chip Carrier Surfaces 470 (1)
Surface Wetting 471 (1)
Cleanliness 471 (1)
Surface energy 471 (1)
Surface roughness 471 (1)
Moisture Effects 472 (1)
Non-JEDEC-classified underfills 472 (1)
JEDEC-classified underfills 472 (1)
Processing 472 (6)
Underfill Flow 474 (1)
Viscosity effects 474 (1)
Filler effects 474 (1)
Filler dispersion 475 (1)
Underfill voids 475 (1)
Fillet formation 476 (1)
Flow process experimentation 476 (1)
Curing 476 (1)
Measurement of extent of cure 476 (1)
Snap cure 476 (1)
Warpage 477 (1)
Flip-Chip-On-Board (FCOB) vs. 477 (1)
Flip-Chip-On-Carrier (FCOC)
Process Control 477 (1)
Throughput Considerations 477 (1)
Effects of Underfill on Reliability 478 (12)
Enhancement Mechanisms 478 (1)
Elimination of stress concentration 478 (1)
Material property contributions 478 (1)
Underfill Reliability Assessment 478 (1)
Reliability background 478 (1)
Accelerated testing vs. field use 479 (1)
conditions
Analysis and modeling 479 (1)
Defects 480 (1)
Manufacturing defects 480 (3)
Time-dependent defects 483 (3)
Effect of delamination on fatigue life 486 (2)
Summary of Underfill Load Response 488 (2)
Recent Developments and Future Directions 490 (3)
Manufacturing Bottlenecks 491 (1)
No-flow underfills 491 (1)
Microwave curing 491 (1)
Reworkable Underfills 492 (1)
Grinding/mechanical methods 492 (1)
Release layer method 492 (1)
Intrinsically reworkable materials 492 (1)
Conclusions 493 (7)
References 493 (7)
Reliability of Die-Level Interconnections 500 (49)
Introduction 500 (1)
Defects 501 (1)
Effect on Failure Distribution 501 (1)
Defect Elimination 501 (1)
Testing 501 (2)
Unchanged Mechanism and Sigma 501 (1)
Different sigma values 502 (1)
Effect of Mechanism on Sigma 502 (1)
Test Failure Criteria 502 (1)
Failure Rates/Distribution 503 (1)
Wearout 503 (1)
Considerations 503 (1)
Approach 503 (1)
Effect of Strain 504 (1)
Failure Distributions 504 (1)
Fatigue 504 (18)
Area Aray Solder Joint Strains 504 (1)
Thermal expansion mismatch strain 504 (1)
Transient gradient induced strain 504 (1)
Relative displacements 505 (1)
Mechanical vs Thermomechanical Stress 505 (1)
Cycles
Mechanical cycles 505 (1)
Thermal cycles 506 (1)
Fatigue Mechanism 506 (1)
Microscopic concept 506 (1)
Macroscopic concept 506 (1)
Modeling Power-Cycle and Thermal-Cycle 506 (1)
Fatigue
Low cycle fatigue 507 (1)
Modifications 507 (1)
Modified fatigue life relationship 507 (1)
Maximum shear strain 508 (1)
Test-to-field relationship 508 (1)
Effect of minicycles (green cycles) 508 (1)
Stress Threshold 509 (1)
Frequency factor 509 (1)
Threshold determination 510 (1)
Below threshold frequency 510 (1)
Above threshold frequency 510 (1)
Strain Components/Variables 511 (1)
Elastic strain 511 (1)
Plastic strain 511 (2)
Transient Strain Factors 513 (1)
Effect of CTE mismatch 513 (1)
Model verification 513 (1)
Combined Transient and Steady State 514 (1)
Effect of Joint Metallurgical Structure 514 (1)
on Sigma
Non homogeneous structures 514 (1)
Homogeneous structures 515 (1)
Mechanistic aspect 515 (1)
Effect of UBM/BSM Relative Diameter 516 (1)
Mid-diameter determination 516 (1)
Effect of Oxygen 516 (1)
Observations 516 (1)
Loss of hermeticity effects 517 (1)
Effect of Footprint 518 (1)
Curvature effect 518 (1)
Package-level application 519 (1)
Effect of Solder Joint Defects 519 (1)
Voids 519 (1)
Partial and total non-wet joints 519 (1)
Excessive gold content 519 (1)
Fatigue Life Enhancement Factors 519 (1)
Eliminate high DNP terminals 519 (1)
Closely matched CTE 519 (1)
Improved joint geometry 520 (1)
Joint solder material 521 (1)
Encapsulation 521 (1)
Corrosion 522 (5)
Introduction 522 (1)
Electrochemical Corrosion 522 (1)
Relative humidity factor 522 (1)
Time-to-failure 522 (1)
Voltage factor 523 (1)
T/RH/B Time-to-failure relationship 523 (1)
Chemical Corrosion 524 (1)
Hermetic packages 524 (1)
Galvanic Corrosion 525 (1)
Diffusion-controlled rate 525 (1)
Corrosion with Polymeric Coatings or Die 525 (1)
Underfill
Lack of adhesion 525 (2)
Diffusion of gaseous reactants 527 (1)
Non-Electrolyte Corrosion 527 (1)
Metal Migration 527 (3)
Mechanism 527 (1)
Necessary conditions 527 (1)
Characteristics 528 (1)
Time-to-Failure 529 (1)
Conductive Reaction Products 529 (1)
Leakage Through Polymer Films 529 (1)
Corrosion/Metal Migration in Semi-Hermetic 530 (1)
Electronic Packages
General Relative Humidity Factor 530 (1)
General Time-to-Fail 530 (1)
Polymer Seals 531 (1)
Oxidation 531 (1)
Introduction 531 (1)
Pb-Sn Solder Oxidation Kinetics 531 (1)
Open module conditions 531 (1)
Restricted oxygen conditions 531 (1)
Example 531 (1)
Oxide-film Analysis 531 (1)
Electromigration 532 (6)
Overview 532 (1)
Failure mode 532 (1)
Microstructural factor 532 (1)
Flip-chip solder bumps 533 (1)
Mechanism 533 (1)
Driving Forces 533 (1)
Key parameters 534 (1)
Time-to-Failure 535 (1)
Mass Transfer Rate 535 (1)
Effect of backflow compressive stress 535 (1)
Empirical Determination of 536 (1)
Electromigration Threshold
Determining Electromigration Kinetics 537 (1)
Example
Time-to-failure 537 (1)
Time and temperature effects on depletions 537 (1)
Velocity and diffusivity 537 (1)
Flip-Chip Solder Joints 537 (1)
Thermomigration 538 (3)
Overview 538 (1)
Flip chips 538 (1)
Mechanism 538 (1)
Pb-Sn Threshold 538 (1)
Indium 539 (1)
Mass Transport Rate 539 (1)
Heat of transport 539 (1)
Time-to-Fail 540 (1)
Thermal gradient threshold 540 (1)
Summary 540 (1)
Soft Errors 541 (4)
Introduction 541 (1)
Alpha Particle Effects 541 (1)
Role of Radioactive Decay 541 (3)
Measurement Technique 544 (1)
Circuit Protection 544 (1)
Air-Path Equivalence 544 (1)
Penetration in common barrier materials 544 (1)
Summary 545 (4)
Appendix 545 (1)
Derivation of Electromigration Model 545 (1)
References 546 (3)
Part II Package-Level Technology 549 (424)
Ceramic and Plastic Pin Grid Array Technology 551 (26)
Introduction 551 (2)
Requirements and Trends of Integrated 551 (1)
Circuit Packaging
Package Pin Count and Miniaturization 551 (1)
PGA Definition 552 (1)
PGA Drivers 552 (1)
Memory vs. logic package requirements 553 (1)
Ceramic Pin Grid Arrays (CPGA) 553 (1)
History/Background 553 (1)
PGA Package Types/Design 554 (4)
Cavity Up/Cavity Down 554 (1)
Grid Arrangement 554 (1)
PGA Substrate Material 554 (1)
Alumina 554 (1)
Aluminum nitride 555 (1)
Other 555 (1)
Design Considerations 556 (1)
Metallized layers 557 (1)
Trace layout 557 (1)
Pin layout 557 (1)
Assembly of CPGA Packages 558 (4)
Die Backbond Attachment 558 (1)
Wire Bonding Processes 558 (1)
Flip Chip Attachment 558 (2)
Other type flip chip connections 560 (1)
Sealing Processes 560 (1)
Seam welding/sealing 560 (2)
Reflow sealing 562 (1)
Glass soldering 562 (1)
Pin Pretinning 562 (1)
Pin Attachment Related Factors 562 (3)
I/O Pad Metallurgy 562 (1)
Alumina/aluminum nitride carriers 562 (1)
Glass ceramic 562 (1)
Pin Material/Overplate 563 (1)
Pin Dimensions 563 (1)
Shank 563 (1)
Head-to-pad diameter factor 563 (1)
Pin Manufacture 564 (1)
Pin Attachment Alloys 564 (1)
High temperature alloys 564 (1)
Low temperature alloys 565 (1)
Pin Attachment 565 (1)
CPGA Pin Rework 565 (1)
CPGA Performance 566 (1)
Electrical Performance 566 (1)
Thermal Performance 566 (1)
High conductivity material 566 (1)
Heat spreaders 566 (1)
Reliability Of CPGA Packages 567 (1)
Test Methods/Conditions 567 (1)
Cavity Dew Point Control 567 (1)
Carrier to Board Connection 567 (1)
Chip-to-Carrier Connection 568 (1)
Plastic Pin Grid Arrays (PPGA) 568 (1)
Background 568 (1)
PPGAs vs CPGAs 569 (1)
Flip Chip PPGA 569 (3)
Application Space 569 (1)
Body Configuration 569 (2)
Standards 571 (1)
PPGA Manufacturing 572 (1)
Core Fabrication 572 (1)
Panel Preparation 572 (1)
Inner Circuit Personalization 572 (1)
Lamination 572 (1)
Hole Drilling 573 (1)
Hole Plating 573 (1)
Defining Outer Circuitry 573 (1)
Outer Pattern/Hole Plating 573 (1)
Resist Stripping 573 (1)
Solder Stripping 573 (1)
Singulation 573 (1)
Pin Attachment 573 (2)
Mechanical Insertion 574 (1)
Surface Mounting 574 (1)
Solder paste printing method 574 (1)
Solder preform method 574 (1)
Solder clad pin method 574 (1)
Microvia Technology 575 (1)
Future Of CPGA/PPGA Packages 575 (2)
Staggered 70-mil Pitch 575 (1)
Pitches of 50-mil and Less 575 (1)
References 575 (2)
Plastic Ball Grid Array 577 (37)
Introduction 577 (1)
Evolution of Laminate Technologies for 577 (1)
Chip Carriers
Marketplace Overview 578 (1)
PBGA Attributes 578 (4)
Package Standards 578 (1)
Marketplace preferences 578 (1)
Body Sizes and I/O Count 578 (1)
Laminate Cross Sections 579 (1)
Wire Bond and Flip Chip Package Options 579 (1)
Chip-up, wire bond/flip chip 580 (1)
Cavity-down, wire bond/flip chip 581 (1)
Variations between cavity substrates 581 (1)
No cavity, flip chip down 581 (1)
PBGA Chip Carriers 582 (3)
Single-Layer Carriers 582 (1)
Wire bonded and flip-chip packages 582 (1)
Two-Layer Carriers 583 (1)
Four-Layer and Greater Carriers 584 (1)
Wiring Technologies 585 (1)
Subtractive technologies 585 (1)
Additive technologies 585 (1)
Build up technologies 585 (1)
Flex technologies 585 (1)
Emerging technologies 585 (1)
Advantages of different wiring 585 (1)
technologies
Wire Bonding Considerations 585 (3)
Geometric Effects 586 (1)
In-line wire bond patterns 586 (1)
Staggered wire bond patterns 586 (1)
Wire-bond lengths 587 (1)
Considerations for Flip Chip on Laminate 588 (5)
High and Dense I/O Requirements 588 (1)
Flip Chip Laminate Carriers 588 (1)
Chip-down design, no option 589 (1)
Low I/O flip-chip carriers 590 (1)
Medium I/O flip-chip carriers 590 (1)
High I/O flip-chip carriers 591 (1)
Design Advantages Using Flip-Chip PBGAs 592 (1)
Fine chip-carrier wiring for flip-chip 592 (1)
designs
Other advantages 593 (1)
Differential pairs 593 (1)
Assembly Process Flows 593 (1)
Laminate Processing 593 (1)
Module Construction 593 (1)
Thermal Performance 594 (3)
Chip Up 594 (1)
Wire bonded packages 594 (1)
Flip-chip bonded packages 594 (1)
Cavity Down 595 (1)
Chip-up versus Cavity-Down Comparison 595 (1)
Die maximum junction temperature 596 (1)
Use of Heat Sinks 596 (1)
Interface integrity vs. reworkability 596 (1)
Modeling 597 (1)
Electrical Performance 597 (2)
Wire Bond or Flip Chip Die 597 (1)
Effect of Chip Carrier Wiring 597 (1)
Tables vs Applications 598 (1)
Impedance Matching 599 (1)
Reliability 599 (6)
Reliability versus Quality 599 (1)
Bonding in PBGA Packages 599 (1)
Wire bonded die 599 (1)
Flip-chip bonded devices 600 (1)
Standard Stress Tests 600 (1)
Acceptable approach 600 (1)
Preconditioning 600 (1)
Accelerated stress tests 601 (1)
Temperature and humidity 602 (1)
Handling Concerns During Test 603 (1)
Insertion and extraction of modules from 603 (1)
sockets
Use of excessive force for retention in 603 (1)
test sockets
Use of abrasive cleaners for BGA solder 603 (1)
balls
Results of Reliability Testing 603 (1)
Fatigue failure 603 (1)
Laminate degradation 604 (1)
Plated through hole related failures 604 (1)
Wire bond die attach issues 605 (1)
Applications 605 (6)
``Simple'' Chip Up and Cavity Down 605 (1)
Designs for Wire-bond Packages
``Complex'' Chip Up and Cavity Down 606 (1)
Designs for Wire-bond Packages
Crossing signal lines 606 (1)
Signal isolation 606 (1)
Tiers for segregation 607 (1)
Card-Level Effects on Package Design 607 (1)
Fine Pitch Applications 607 (1)
Reduced wire diameter implications 607 (1)
Tradeoffs between staggered and in-line 608 (2)
wire bonding
Flip-chip applications 610 (1)
Low I/O flip-chip applications 610 (1)
Medium I/O flip-chip applications 611 (1)
High I/O flip-chip applications 611 (1)
Future Extension of PBGA Packages 611 (3)
Limitations of Wire Bond Packages 611 (1)
Benefits of Flip-Chip Applications 611 (1)
Challenges to Overcome for Flip Chip PBGA 612 (1)
Packages
Acknowledgments 612 (1)
References 612 (2)
Tape Ball Grid Array 614 (42)
Introduction/Background 614 (3)
Development History 615 (1)
Package Demand 616 (1)
Package Design 617 (4)
Overview 617 (1)
Package Standards 617 (1)
Body size, I/O count 617 (1)
Ball coplanarity 618 (2)
Effect of Cavity Location/Die Size on I/O 620 (1)
Count
Package Elements 621 (10)
Flex Tape 621 (1)
Design aspects 621 (4)
Dielectric 625 (1)
Single-level metal tape 626 (1)
Two-level metal tape 627 (1)
Adhesiveless flex tape 627 (1)
Enhanced wireability 628 (1)
Stiffeners 629 (1)
Construction 629 (1)
Adhesive 629 (1)
Solder Ball 630 (1)
Component Manufacture 631 (9)
Various Process Flows 631 (1)
Wire bond, low-melt solder balls 631 (1)
T/C bonded die, low-melt solder balls 631 (1)
High-melt carrier solder balls 631 (1)
Stiffener/Cover Plate Attachment 632 (1)
Die Attach 633 (1)
Die-to-Flex Interconnection 633 (1)
Wire bonds 633 (2)
ILB thermocompression bonding 635 (1)
Solder-bump flip chip bonding 636 (1)
Encapsulate/Overmold 637 (1)
Ball Attachment 637 (1)
Pad definition 637 (1)
Etched opening 638 (1)
Partially melted balls 638 (1)
Ball-Attachment Integrity 639 (1)
Ball shear test 640 (1)
Factors affecting strength 640 (1)
Thermal Performance 640 (6)
Brief Overview 640 (1)
Junction-to-ambient thermal resistance 641 (1)
Internal thermal resistance 641 (1)
External thermal resistance 642 (1)
TBGA Package Dissipation 643 (1)
Card effect 643 (1)
Natural vs. forced convection 643 (1)
Heat sinks 643 (1)
Modeling 643 (3)
Electrical Performance 646 (2)
Effect of Body Size, Trace Length 646 (1)
Single-Level Enhancements 647 (1)
Two-Level Enhancements 647 (1)
Reliability 648 (3)
Defect-Driven Failure 648 (1)
Solder Joint Fatigue 649 (1)
Effect of Absorbed Moisture 650 (1)
Adhesion factor 650 (1)
TBGA Testing 651 (1)
Future/Extendability 651 (5)
Future Requirements 651 (1)
Multilayer Flex Tape 652 (1)
Electrical Enhancements 652 (1)
Thermal Enhancements 652 (1)
Cost Competitiveness 652 (1)
References 652 (4)
Ceramic Ball and Column Grid Arrays 656 (46)
Introduction 656 (1)
Performance Drivers for CBGA and CCGA 656 (1)
Components
Process Drivers for CBGA and CCGA 657 (1)
Components
Description of Dual-Metal CBGA Packages 657 (7)
CBGA Chip Carrier 657 (1)
Offerings 657 (1)
Construction 658 (1)
Materials aspects 659 (1)
Die Interconnection and Encapsulation 660 (1)
Options
Wire bond attachment/layout 660 (1)
Wire bond thermal factors 660 (1)
Wire bond encapsulation factors 661 (1)
Flip chip ceramic chip carrier combination 662 (1)
Die underfill 662 (1)
Encapsulation options 662 (1)
Other component attachments 662 (1)
Package Interconnection Structure 662 (2)
CBGA Dual Metal Optimization 664 (6)
CBGA Joint Stress Distribution 664 (1)
Solder Considerations 664 (1)
Solder deformation 664 (2)
Properties of material candidates 666 (2)
Ball and Fillet Combination Evaluations 668 (1)
Joints based on 97Pb-3Sn ball 668 (1)
Joints based on 90Pb-10Sn ball 669 (1)
Geometry Versus Material Effects 669 (1)
Dimpled Ball Grid Array 670 (2)
DBGA Chip Carrier 671 (1)
Dimple Formation 671 (1)
Ball Formation 672 (1)
DBGA Reliability Factors 672 (1)
Ceramic Column Grid Array 672 (3)
CCGA Chip Carrier 672 (1)
Die Interconnection 673 (1)
Wire/Cast Package Interconnection 673 (2)
Structures
Effect of Pitch Reduction 675 (1)
Strain Dissipation 675 (1)
Encapsulation 675 (1)
Package Standards and Offerings 675 (2)
CBGA JEDEC Standards 675 (1)
CCGA JEDEC Standards 676 (1)
Test and Burn-In 677 (1)
CBGA 677 (1)
CCGA 677 (1)
Choosing CBGA or CCGA 677 (1)
Advantages and Disadvantages of CBGA and 678 (3)
CCGA Packages
Interconnection Density 678 (1)
Other packages 678 (1)
CBGA versus other packages 678 (1)
Full array advantage 678 (1)
Thermal Performance 679 (1)
Thermal paths 679 (1)
Die-backside conduction 679 (1)
CBGA versus WB-PGA 680 (1)
Electrical Performance 680 (1)
Disadvantages 680 (1)
Printed Circuit Board Requirements 681 (3)
PCB Joining Pads 681 (1)
Plated Through Hole (PTH) 682 (1)
Wiring Trace/Solder Mask 682 (1)
Card Surface Finishes 683 (1)
Ground Rules 683 (1)
Lines and spaces 683 (1)
Layup/flatness 684 (1)
Material/layout 684 (1)
Card Assembly Process Requirements 684 (1)
Package Interconnection Reliability 685 (1)
Geometric Factors 685 (1)
CBGA 685 (1)
CCGA 685 (1)
Metallurgical Factors 685 (1)
CBGA joints 685 (1)
Single-metal solder joints 686 (1)
CCGA joints 686 (1)
Additional Design Factors 686 (1)
Mechanical Robustness 686 (1)
Solder Ball Attachment Processes 686 (5)
Process Overview 686 (1)
Manual Processing 687 (1)
Solder-ball fixtures 687 (1)
Solder paste 687 (1)
Solder-paste application 687 (1)
Solder-ball alignment 688 (1)
Reflow attachment 689 (1)
Automated Processing 689 (1)
Screened solder paste 689 (1)
Solder preform process 689 (1)
Reflow attachment 690 (1)
Solder Ball Rework 690 (1)
Solder Column Attachment Processes 691 (2)
Wire Column Attachment 691 (1)
Cast Column Attachment 691 (1)
Column Rework 692 (1)
Wire Versus Cast Columns 692 (1)
Cast rework advantage 692 (1)
Wire assembly advantage 692 (1)
CLASP Column Attachment Process for 693 (1)
Automation
Shipping Containers 693 (1)
CBGA Shipping Containers 693 (1)
CCGA Shipping Containers 693 (1)
Application Examples 694 (3)
Future Use of CBGA and CCGA Packages 697 (1)
Summary 697 (5)
Acknowledgments 698 (1)
References 698 (4)
Chip Scale Package Technology 702 (60)
Introduction 702 (2)
Background 702 (1)
Utilization 702 (1)
CSP vs. DCA/Conventional Packages 703 (1)
This Chapter 704 (1)
Chip Scale Package Definition 704 (1)
Current Practice 704 (1)
Package Design Options 704 (10)
Distinction From DCA 704 (1)
Lead Frame 704 (1)
Rigid-Interposer Type 705 (1)
Organic 706 (2)
Ceramic 708 (1)
Flexible Interposer Type 709 (1)
Three-layer tape version 709 (1)
Enhanced flex 710 (1)
Floating pad technology 710 (1)
Double-sided metallized films 711 (1)
Wafer Level Process 711 (1)
General process/construction schemes 711 (2)
Ultra CSP 713 (1)
Wave technology 713 (1)
Enhanced BCC packages 713 (1)
Commercially-available CSPs 714 (1)
Comparison of CSP Designs 714 (1)
CSP Board-Related Issues 714 (6)
Standardization and Availability 714 (2)
Die shrink considerations 716 (1)
Board CTE 716 (1)
CTE-Compensated Boards 716 (1)
Solder Mask Issues 716 (1)
Solder mask defined pad (SMD) 717 (1)
Non-solder mask defined pad (NSMD) 717 (1)
Mounting Pad Design 718 (1)
Build-up Technology 718 (1)
Surface Finish 719 (1)
Solder joint embrittlement 719 (1)
Reflow profile modification 720 (1)
Pressure contacts 720 (1)
Pre-Assembly Issues 720 (2)
Board Moisture 720 (1)
Moisture removal 720 (1)
PWB Inspection 720 (1)
Planarity 721 (1)
Component Inspection 721 (1)
Missing solder balls 721 (1)
Debris 721 (1)
Component Handling/Storage 722 (1)
CSP-to-Board Assembly 722 (9)
Circuit Card Assembly Process Flow 722 (2)
Stencil Design For Paste Printing 724 (1)
Area ratio 724 (1)
Aperture ratio 724 (1)
Apertures 724 (1)
Step downs 724 (1)
Solder Paste 724 (1)
Solder Paste Printing 725 (1)
Fine line printing 726 (1)
Paste vs. flux 726 (1)
Solder-Paste Print Inspection 726 (1)
Stand-alone systems 726 (1)
Component Placement 727 (1)
Required accuracy for CSPs 727 (1)
Vision systems 727 (1)
Paste contact 727 (1)
Placement Inspection 727 (1)
Reflow Attachment/Effects 728 (1)
Factors that affect profile 728 (1)
Profile 728 (1)
Atmosphere 728 (1)
Effects of moisture 728 (1)
Cleaning 729 (1)
Assembly Inspection 730 (1)
Visual inspection 730 (1)
X-ray inspection 730 (1)
Acoustic microscopy 730 (1)
Voids 730 (1)
CSP Rework 731 (5)
Rework Equipment/Tooling 732 (1)
Thermal Profile Monitors 732 (1)
Thermocouple placement 733 (1)
Thermal profile 734 (1)
General Rework Process Flow 734 (2)
Reliability of CSP Assemblies 736 (12)
Packaging Levels 737 (1)
Chip Carrier Effects 737 (1)
Board Effects 737 (1)
Thickness 737 (10)
Single versus double-sided assembly 747
CTE mismatch 737 (3)
Surface Finish Effects 740 (1)
Standard finishes 740 (1)
Metallurgical factors 740 (1)
Effects of Solder Joint Voids 741 (1)
A problem or not 741 (1)
Influences 741 (1)
Standards 742 (1)
Underfill Considerations 742 (1)
Reliability Test Results 742 (1)
Expansion mismatch effects 743 (1)
Laminate Failures 743 (1)
Effect of key factors 743 (1)
Reliability Comparisons 744 (1)
Multiple factor variation 744 (3)
Assembly Guidelines to Optimize 747 (1)
Reliability
Other Key Enabling Technologies 748 (1)
Build-up Technology 748 (1)
Test and Burn-in Capability 748 (1)
Need test sockets/carriers 748 (1)
CSP-Related-Consortia Activities 749 (1)
CSP-Related-Applications 749 (2)
Some Major Suppliers 751 (1)
New Developments 751 (1)
Future Developments 751 (2)
SLC Micro-Via Board Construction 752 (1)
Lead Free Solders 752 (1)
Alternative Board Materials 753 (1)
Summary 753 (9)
Acknowledgments 753 (1)
Suggested Reading 754 (1)
References 754 (8)
Assembly of Area Array Components 762 (42)
Introduction 762 (2)
Surface Mount Technology Assembly 762 (1)
Direct Chip Attach 762 (2)
Advantages/Disadvantages 764 (1)
Standards 764 (1)
Assembly Process Flow 764 (2)
Hybrid Assembly 764 (1)
Double-sided Assembly 765 (1)
Direct Chip Attach Assembly 766 (1)
Pre-Assembly Handling Procedures 766 (4)
Component Moisture Sensitivity 766 (1)
Printed Circuit Board Considerations 767 (1)
Pad size/configuration 768 (1)
Pad solderability 768 (1)
Proximity of components 769 (1)
Board physical characteristics 769 (1)
Solder Paste and Application 770 (12)
Materials 770 (1)
Solder paste overview 770 (1)
Solder alloy powder 771 (1)
Flux 771 (1)
Stencils 772 (2)
Squeegee blades 774 (2)
Screen Printer Tooling 776 (1)
Component Solder Paste Requirements 776 (1)
General requirements 776 (2)
CBGA requirements 778 (1)
CCGA requirements 779 (1)
PBGA solder paste requirements 780 (1)
TBGA requirements 780 (1)
CSP requirements 780 (1)
Flip chip direct-attach requirements 781 (1)
Acceptability Criteria 781 (1)
Inspection Techniques 781 (1)
Component Placement 782 (6)
Placement Methods 782 (1)
Component recognition/alignment 782 (1)
Vision component recognition 782 (1)
Tooling and Process Parameters 783 (1)
Component positioning systems 783 (1)
Overhead gantry style 783 (1)
Chip shooters 783 (2)
Modular placement systems 785 (1)
Vision systems 786 (1)
Area array component placement 786 (1)
Placement Accuracy 787 (1)
Solder Reflow 788 (3)
Reflow Metods 788 (1)
Vapor phase reflow 788 (1)
Infrared reflow 788 (1)
Forced convection reflow 788 (2)
Reflow Process 790 (1)
Preheat 790 (1)
Pre-reflow soak 790 (1)
Reflow 790 (1)
Typical reflow profile 790 (1)
Thermal Profile Monitoring 790 (1)
Cleaning 791 (3)
Type Residues 791 (2)
Cleaning Methods 793 (1)
Cleaning Adequacy and Testing 794 (1)
Area Array Reflow Yields 794 (1)
Solder Joint Acceptability/Defective 794 (3)
Conditions
Physical Criteria 794 (1)
Defects 794 (1)
Opens 794 (2)
Bridging 796 (1)
Voids 796 (1)
Poor joint structure 796 (1)
Inspection/Test 797 (4)
Visual Inspection 798 (1)
Radiation-Based Techniques 798 (1)
Infrared 798 (1)
Ultrasound 798 (1)
X-rays 798 (3)
Electrical Test 801 (1)
Future Directions 801 (3)
Component Features 801 (1)
Processes 802 (1)
Materials 802 (1)
Acknowledgments 802 (1)
References 802 (2)
Area Array Component Replacement Technology 804 (34)
Introduction 804 (1)
Business Case for Replacement 805 (2)
Assembly Defect Comparison 805 (1)
Example 1 805 (1)
Reasons for Rework 806 (1)
Rework Decision 806 (1)
Example 2 806 (1)
Analysis 807 (1)
General Replacement Process Flow 807 (1)
Process Flow 807 (1)
Validation 808 (1)
Limitations 808 (1)
Preliminary Activities 808 (4)
Board Preparation 808 (1)
Prebake moisture-sensitive components 808 (1)
Remove heat-sensitive components 809 (1)
Remove heat sinks/intefering components 809 (1)
Protecting heat-sensitive components 809 (2)
Thermal Profile Development 811 (1)
Neighboring component joints 811 (1)
Product-like monitors 811 (1)
Thermocouple layout 812 (1)
Role of flux 812 (1)
Component Removal 812 (2)
Global Preheat 812 (1)
Molten Solder Joints 813 (1)
Component Separation from Card 814 (1)
Manual/automatic modes 814 (1)
Gravity 814 (1)
Site Preparation 814 (7)
Solder Dress Methods 814 (1)
Chisel-tip irons/solder suckers 814 (1)
Directed molten solder 815 (1)
Localized Board Warpage 816 (1)
Key contributing factors 816 (1)
Planarizing warped sites 817 (1)
Site Planarity 817 (1)
Requirement 817 (1)
Planarity measurement 818 (1)
Insufficient Pad Coverage 818 (1)
Rework Dull Appearing Pads 819 (1)
Replacement Solder 819 (1)
Dip process 819 (1)
Stencil solder on site 820 (1)
Stencil solder on module leads 820 (1)
Dispense solder paste 820 (1)
Solder preforms 821 (1)
Solder volume requirements 821 (1)
Component Replacement 821 (4)
Component Inspection 822 (1)
Option: Flux or Add Solder 822 (1)
Component Placement 822 (1)
Component alignment requirements 822 (1)
Tool optics 822 (1)
Component picking 823 (1)
Reattach Replacement Components 824 (1)
Heat-shield/global preheat 824 (1)
Reflow cycle/heat spreader 824 (1)
Cool down cycle 825 (1)
Remove heat shield 825 (1)
Clean excess flux 825 (1)
Successful Replacement Verification 825 (1)
Assembly Completion 825 (1)
Heat-Sensitive Component Installation 826 (1)
Heatsink/Interfering Component 826 (1)
Installation
Final Clean 826 (1)
DCA and CSP Rework 826 (2)
Die Removal 826 (1)
Solder Replenishment 827 (1)
Coining 827 (1)
Placement 827 (1)
Reflow 827 (1)
Underfill 827 (1)
Inspection (Optional) 828 (1)
Visual/Low Magnification 828 (1)
X-ray 828 (1)
Component Reuse 828 (5)
Single Joint vs. Total Matrix Approach 829 (1)
Remove Joined Module 829 (1)
Dress Component Lead Ends 829 (2)
Dress Board Site Pads 831 (1)
Board Low Temperature Attachment 831 (1)
Process requirements 831 (1)
Rework processes 831 (1)
Lead Replacement 832 (1)
Replacement Tools 833 (2)
Heating Methods for Tools 834 (1)
Modes of preheating 834 (1)
Hot gas nozzle designs 834 (1)
Site Redress Tools 834 (1)
Fluxing Methods 834 (1)
Future Trends 835 (3)
Acknowledgments 835 (1)
References 835 (3)
Product Connector Technology 838 (44)
Introduction 838 (1)
Pins 838 (1)
Migration to Cost Performance 839 (1)
This Chapter 839 (1)
Generic BGA/LGA Connector Assemblies 839 (3)
Land Grid Array (LGA) 839 (1)
Chip carrier and board pads 839 (1)
Hardware 840 (1)
Strain dissipation 840 (1)
Pluggable GBA 840 (1)
Strain dissipation 841 (1)
Engagement 841 (1)
BGA/LGA Package Demount Capability 842 (1)
Advantages 842 (1)
Upgrades 842 (1)
System bring-up 842 (1)
Economic leverage 842 (1)
Enhanced reliability 843 (1)
Disadvantages 843 (1)
Demountable Connector Design Goals 843 (1)
Board Space 843 (1)
Keep-Out Area 844 (1)
Assembled Height Profile 844 (1)
Weight 844 (1)
Insertion Cycles 844 (1)
Unobstructed Top Surface 844 (1)
Ease of Operation 844 (1)
Connector System Requirements 844 (3)
JEDEC Specifications 844 (1)
Physical Characteristics 845 (1)
Electrical Requirements 845 (1)
Metallurgical Requirements 846 (1)
Component I/Os 847 (1)
Ball Grid Array (BGA) 847 (1)
Single solder 847 (1)
Dual solder 847 (1)
Strain dissipation 847 (1)
Land Grid Array (LGA) 847 (1)
Board finishes 848 (1)
SMT attached connectors 848 (1)
Non-Attached Connectors 848 (1)
Mixed Metallizations 848 (1)
Stress-Related Issues 848 (11)
LGA Structural Loading 849 (1)
Source of stress 849 (1)
Flexure during chip-carrier actuation 849 (2)
Areas of concern 851 (1)
Conditions which increase stress 852 (1)
Chip-Carrier Strength Issues 852 (1)
Fracture mechanics 852 (1)
Factors which influence chip-carrier 853 (1)
strength
Effect of sustained vs. static loads 854 (1)
Strength measurement and design targets 854 (1)
Other Materials of Interest 854 (1)
Polymers 855 (1)
Solders 855 (1)
Guidelines for a Low-Stress LGA Design 855 (1)
Collinearity of I/Os and seal band 856 (1)
Chip-carrier thickness 856 (1)
Chip-carrier modulus 856 (1)
Die size 856 (1)
Seal band modulus 857 (1)
Die/lid gap material 858 (1)
Spring characteristics 858 (1)
Testing 859 (4)
Standard Industry Tests 859 (1)
Purpose/scope 860 (1)
Screen Test 860 (2)
Test Hardware 862 (1)
Product Testing 862 (1)
General Test Results 863 (3)
BGA Connectors 863 (1)
Solder ball/solder-coated contacts 863 (1)
Solder-coated hard balls 863 (2)
Precious-metal coated hard balls 865 (1)
LGA Connectors 866 (1)
Commercially-Available Connector Types 866 (11)
Helical Springs 866 (1)
Wire Button Spring 867 (1)
Background 867 (1)
Description 867 (1)
Operation 868 (1)
Electrical characteristics 868 (1)
Thermal/environmental characteristics 868 (1)
Mechanical characteristics 869 (1)
Stamped and Formed Springs 869 (1)
Metal spring materials 869 (1)
Stress relaxation 870 (1)
Conductivity 870 (1)
Formability 870 (1)
C-shaped springs with and without shunts 870 (1)
E-shaped spring 871 (1)
Inverted U-shaped spring 871 (1)
BGA zero-insertion-force spring 872 (1)
Polymer-Based Systems 873 (1)
Polymer interposer 873 (2)
Polymer contact elements 875 (1)
Hard/Piercing Particle Contacts 875 (1)
Need for high density and demount 876 (1)
capability
Piercing contact example 876 (1)
Other Designs 877 (1)
Future Trends 877 (5)
Reduced Pitches and Contact Force 877 (1)
Enhanced Portability and Electrical 877 (2)
Characteristics
References 879 (3)
Board-Level Area Array Interconnect 882 (64)
Reliability
Introduction 882 (1)
Board Level Versus Die Level 882 (1)
Mechanisms 882 (1)
Crack propagation distance 882 (1)
Void formation 883 (1)
Stain levels 883 (1)
Purpose 883 (1)
Direct Chip Attach (DCA) 883 (1)
Fatigue Aspects 883 (1)
Corrosion Aspects 884 (1)
Fatigue Failure 884 (1)
Mechanism 884 (1)
Creep factor 884 (1)
Importance of card/board material 884 (1)
Sensitivity to Parameters 884 (1)
Ball vs column I/Os 884 (1)
Pressure contacts 885 (1)
Corrosion susceptibility 885 (1)
Fatigue Life Prediction 885 (5)
Shear and Tensile Strain Model Transformer 885 (1)
Creep Consideration 885 (1)
Single Versus Double-Sided Card 885 (1)
Generic Strain 886 (1)
Tensile Strain 886 (1)
Single vs double-side population 886 (1)
Effect of defects 887 (1)
Effect of Dimensional Factors on Joint 888 (1)
Shear Strain
I/O location 889 (1)
Generic Fatigue Model 889 (1)
Factors affecting tensile strain 889 (1)
Relationship for die or board-level joints 890 (1)
Parametric Effects on Fatigue Life 890 (3)
Joint Diameter 890 (1)
Diameter factor 890 (1)
Process and Other Influences 890 (1)
Generic Fatigue Life Relationships 890 (1)
Solder Volume 891 (1)
Determination 891 (1)
Unequal Terminal Pads 891 (1)
Footprint Effects 891 (1)
Effect of depopulation 891 (1)
DNP shift 892 (1)
Metallurgical Factors 892 (1)
Effect of Process 892 (1)
Voids 892 (1)
Other defects 893 (1)
Introduction to Board-Level Reliability 893 (3)
CTE Mismatch and Area Array Package 893 (1)
Solder Joint Fatigue
Temperature excursions in electronic 894 (1)
systems
Power versus thermal cycling 894 (1)
Board Bending Effects 895 (1)
Heat Sink Effects 895 (1)
Mechanical Shock Effects 895 (1)
Vibrational Effects 896 (1)
Solder Joint Reliability Requirements by 896 (3)
Application
Consumer and Handheld Applications 896 (1)
Computing and Telecommunications 897 (1)
Infrastructure Applications
Automotive Applications 898 (1)
Industrial Applications 898 (1)
Accelerated Testing Methodology 899 (6)
Accelerated Test Conditions for Solder 900 (1)
Joint Reliability
Accelerated Testing 900 (1)
Replicate product form factor 900 (2)
Monitoring 902 (1)
Testing 902 (2)
Biased Temperature and Humidity Testing 904 (1)
Statistics of Solder Joint Failure 905 (5)
The Two-Parameter Weibull Distribution 905 (1)
The Three-Parameter Weibull Distribution 906 (1)
and Failure-Free Time
The Log-Normal Distribution 907 (1)
Comparison and Applicability of 907 (1)
Distributions
Statistical Significance and the 908 (1)
Comparison of Data Sets
Example 909 (1)
Select correct metric 910 (1)
Wire-Bond Plastic BGA Solder Joint 910 (11)
Reliability
Wire-Bond Plastic BGA Package Construction 911 (1)
Effect of Soldermask Versus Copper 912 (1)
Defined Solder Pads
Defect examples 913 (2)
Performance differences 915 (1)
Effect of PBGA Chip Carrier Thickness 916 (1)
Effect of Die Size and Perimeter Versus 916 (1)
Full Array PBGA
Perimeter Versus Full Array PBGA 916 (3)
Effect of PBGA Pitch, Solder Ball and Pad 919 (1)
Diameter
Solder ball---package pad diameter 919 (1)
Perimeter---thermal pad diameter 919 (1)
Effect of pitch 920 (1)
Other Effects 920 (1)
Thermally-Enhanced PBGA Solder Joint 921 (2)
Reliability
Tape Ball Grid Array Solder Joint 923 (1)
Reliability
Flip-Chip Plastic BGA Solder Joint 923 (4)
Reliability
Device-to-Carrier Attachment 925 (1)
Test Versus Use Conditions 925 (1)
Flip-Chip Plastic BGA Construction 925 (1)
Effect of Construction on Flip-Chip PBGA 926 (1)
Solder Joint Reliability
Several constructions 926 (1)
Ceramic BGA and CGA Solder Joint Reliability 927 (8)
Ceramic BGA and CGA Package Construction 927 (1)
Effect of CBGA Body Size and Distance 928 (1)
from the Neutral Point
Board Attach, Solder Paste Volume 928 (1)
Requirements and Effects
Effect of Ceramic Chip Carrier Thickness 929 (1)
Thickness adjustment to Coffin-Manson 929 (2)
relationship
Reliability Improvement with Solder 931 (1)
Columns and Column Interposers
Solder column types 931 (1)
Reliability improvement with columns 931 (1)
Effect of Board CTE on CBGA Solder Joint 932 (1)
Reliability
Effect of Ceramic CTE on CBGA Solder 932 (1)
Joint Reliability
Die Influence on CBGA-to-Board Reliability 933 (1)
CBGA Solder Joint Failure Modes 933 (2)
CCGA Solder Joint Failure Modes 935 (1)
Solder Column Interposer Solder Joint 935 (1)
Failure Modes
Overview of Field Life Prediction 935 (2)
Methodologies
Coffin-Manson and Norris-Landzberg 936 (1)
Relationships
A prediction example 936
IPC-SM-785 932 (5)
Finite Element Modeling 937 (1)
PC Board Construction and Material 937 (2)
Considerations for Solder Joint Reliability
Effect of PCB CTE 937 (1)
Other board materials 937 (1)
PCB Pad Configuration and Diameter 938 (1)
SMD pads 938 (1)
NSMD pads 938 (1)
PCB and Chip Carrier Surface Finish 939 (1)
Effects
HASL vs OSP 939 (1)
Assembly Effects on Solder Joint Reliability 939 (7)
Effect of PBGA Solder Joint Voiding 940 (1)
Effect of Multiple Reflows 940 (1)
Board finishes 940 (1)
Considerations 940 (1)
Cleaning Under Area Array Packages 941 (1)
Board Flexure During Assembly 941 (1)
Singulation 941 (1)
Electrical testing 942 (1)
Rework of Area Array Assemblies 942 (1)
Acknowledgments 942 (1)
References 942 (4)
Chip Scale Package Assembly Reliability 946 (27)
Introduction 946 (2)
CSP Evolvement 946 (1)
Die shrinkage 946 (1)
Unresolved issues 946 (1)
Implementation Challenges 947 (1)
Lack of test vehicle/test data 947 (1)
Lack of design guidelines 947 (1)
Need for microvia PWB 947 (1)
I/O limitation 947 (1)
Reliability Scope 947 (1)
Reliability Issues 948 (2)
Tests Methods for Reliability Evaluation 948 (1)
Accelerated thermal cycle (ATC) test 948 (1)
Performance-Based Assurance Requirement 948 (1)
Unique tests 949 (1)
Non traditional approaches 949 (1)
Stress-Induced Solder Joint Damage 949 (1)
CTE mismatch/solder creep 949 (1)
Increased thermal cycle 949 (1)
Optimized CTE 949 (1)
Accommodating strain 950 (1)
Reliability Factors 950 (1)
Design 950 (1)
Solder mask 950 (1)
Pad size 950 (1)
Interposer Variables 950 (1)
Die bond 950 (1)
Thickness 950 (1)
Materials 950 (1)
Die-size 950 (1)
Solder Ball 950 (1)
Solder composition 950 (1)
Ball attachment 951 (1)
Assembly Variables 951 (1)
Solder joint height 951 (1)
Underfill 951 (1)
Double reflow 951 (1)
Early Studies 951 (4)
Manufacturers Studies 951 (4)
User Study 955 (1)
Dynamic Behavior 955 (1)
Failure Prediction 955 (1)
Failure Mechanisms 955 (1)
Misleading Predictions 955 (1)
Design/DNP Effects 956 (1)
Consortia Pre-Production CSP Assemblies 956 (10)
Studies
Hardware 956 (1)
Printed wiring board (PWB) CSP assembly 956 (1)
studies
Packages 956 (1)
Assembly 956 (1)
Comparative Stress Testing 957 (1)
Approach/Objectives
Accelerated Thermal Cycle Tests I 957 (1)
Failure criterion 957 (1)
BGA results 957 (1)
Accelerated Thermal Cycle Test II 957 (3)
Results 960 (1)
Ball Shear 961 (1)
Test procedures 961 (1)
Results before isothermal aging 962 (1)
Results after isothermal aging 963 (1)
Assembly Quality 964 (1)
Quality of solder joints 965 (1)
Pull test as-assembled 965 (1)
Pull test after thermal cycling 965 (1)
Production Assembly Studies 966 (3)
Wide Distribution of Daisy-Chain 966 (2)
Resistances
Accelerated Thermal Cycle (ACT) Test 968 (1)
Chip-on-flex assembly failures 968 (1)
X-ray inspection 968 (1)
Effects of single and mirror-imaged 968 (1)
double-sided assembly
Summary/Conclusions 969 (4)
Acknowledgments 970 (1)
References 971 (2)
Part III Base Technology 973 (172)
Area-Array Design Principles 975 (36)
Introduction 975 (5)
Silicon-driven Challenges 976 (1)
Area-array Enablers 977 (1)
Flip-chip interconnection 977 (1)
Operational considerations 977 (1)
Interconnects and their properties 978 (2)
Design Objectives 980 (7)
Packaging Density and Signal Propagation 980 (1)
Density vs. material characteristics 981 (1)
Electrical parasitics 981 (1)
Case Study of a Memory Interconnection 982 (1)
Conditions investigated 982 (1)
Effect of frequency 983 (1)
Approaches to Signal Integrity Enhancement 983 (1)
System bus issues and design approaches 984 (1)
Point-to-point interconnection 984 (1)
Summary 985 (1)
FC Area-array Impact on Chip Design 985 (1)
High-power currents 985 (1)
Worst-case situation 985 (1)
Lowest acceptable VDD case 985 (1)
I/O density 986 (1)
Flip-chip drivers 986 (1)
Chip Design For Flip-Chip Interconnections 987 (5)
Choices 987 (1)
Example 1 988 (1)
Example 2 989 (1)
Example 3 989 (1)
Peripheral Array Voltage Drop 989 (2)
Area-array Voltage Drops 991 (1)
Example: power supply wiring requirements 991 (1)
Signal Distribution Considerations 991 (1)
Design limitations 992 (1)
C4 Impact on Module Design 992 (5)
I/O Considerations 992 (1)
Cost Considerations 992 (1)
Die shrink 993 (1)
Other Considerations 993 (1)
Thermal Implication of C4 Use with SCMs 994 (1)
First-level Package Structures 994 (1)
Single chip modules 994 (1)
Multi-chip modules 995 (1)
MCM attributes 996 (1)
Flip-chip replacement capability 996 (1)
Few chip modules 997 (1)
Module-level Electrical Design Issues 997 (10)
Signal Propagation 997 (1)
Tradeoffs 998 (2)
Electronic Switching Noise Overview 1000 (1)
Coupled noise 1000 (1)
Simultaneous switching or ΔI noise 1001 (2)
Δ-I noise modeling and simulation 1003 (1)
SCM technology comparisons 1003 (4)
ΔI noise impact on system 1007 (1)
performance
Chip Carrier-to-Board Interconnections 1007 (1)
Summary and Conclusions 1007 (1)
Future Directions 1008 (3)
Acknowledgments 1009 (1)
References 1009 (2)
Area Array Leverages: Why and How to Choose a 1011 (20)
Package
Introduction 1011 (1)
Dimensional-Related Advantages 1011 (2)
Die I/O: Perimeter vs Area Array 1011 (1)
Die Support Area 1012 (1)
Relative Array Package Sizes 1012 (1)
Chip Carrier Options 1013 (2)
Flip Chip and Wire Bond 1013 (1)
Ceramic and Organic 1014 (1)
SCM and MCM 1015 (1)
Chip Scale Packaging and Direct Chip 1015 (1)
Attach
Electrical Performance 1015 (6)
Higher Frequency 1015 (1)
Chip Power Distribution 1015 (1)
Current/resistance effects 1016 (1)
Inductance/current change effects 1016 (1)
Superior current distribution 1016 (1)
Frequency-based choices 1017 (1)
Increased Bandwidth 1017 (1)
Increased data rate 1017 (1)
Increased data bus width 1018 (1)
Minimizing Delay---An Example 1018 (1)
Discontinuities 1018 (1)
Example of package interconnection choices 1019 (1)
Area array enhancement 1020 (1)
Thermal-Related Factors 1021 (2)
Dissipation Requirements 1021 (1)
Dual path 1022 (1)
Space and Spacing Implications 1022 (1)
Internal resistance 1022 (1)
External resistance 1022 (1)
Thermomechanical Concerns 1022 (1)
Package CTE considerations 1023 (1)
Other Considerations 1023 (1)
Technology Innovation and Development 1023 (1)
Cycle
Evolution vs revolution 1023 (1)
New materials 1024 (1)
Maintenance and service 1024 (1)
Cost 1024 (2)
Chip Carriers 1025 (1)
Printed Circuit Boards 1025 (1)
Need for more density/wiring planes 1025 (1)
Direct chip attach 1026 (1)
Selection Approaches 1026 (4)
Chip Footprint 1026 (1)
I/O count 1026 (1)
Die shrink strategy 1026 (1)
Performance 1027 (1)
Chip Carrier Choice 1027 (1)
Single chip modules or multi-chip modules 1027 (3)
Summary 1030 (1)
References 1030 (1)
Interconnections for High-Frequency 1031 (18)
Applications
Introduction 1031 (1)
Definition 1031 (1)
Flip Chip for High-Frequency 1031 (1)
Advantages over wire bond 1031 (1)
Drivers: assembly/performance 1032 (1)
Variations 1032 (1)
Activities 1032 (1)
Die Design Issues 1032 (2)
General Construction---Microstrip vs. 1032 (1)
Coplanar
Configuration 1032 (1)
Design tools 1033 (1)
Cost 1033 (1)
Material 1033 (1)
Bumping GaAs 1034 (2)
Under Bump Metallurgy (UBM) 1034 (1)
GaAs chips 1034 (1)
InP chips 1034 (1)
Bump Materials 1034 (1)
Gold 1034 (1)
Gold/tin alloys 1035 (1)
Silver 1035 (1)
Indium and its alloys 1035 (1)
Adhesives for bumping 1035 (1)
Deposition Methods 1035 (1)
Plating 1035 (1)
Evaporation 1036 (1)
Studs 1036 (1)
Carrier bumping 1036 (1)
Bond Wire Free Joining Without Bumping 1036 (1)
Joining Methods 1036 (2)
Solder Reflow 1036 (1)
High/low melt bumps 1036 (1)
Self alignment 1037 (1)
Non-melting bumps 1038 (1)
Thermocompression and Thermosonic Joining 1038 (1)
Adhesive Joining 1038 (1)
Reliability 1038 (1)
Encapsulation 1038 (1)
Inhomogeneity 1038 (1)
Underfills and Glob Tops 1039 (1)
Examples 1039 (1)
Packages For High-Frequency Applications 1039 (2)
Requirements 1039 (1)
Chip Carriers 1039 (1)
Preferred Package 1040 (1)
Examples 1040 (1)
Chip-on-Flex Example 1040 (1)
Electrical Performance 1041 (1)
Requirements 1041 (1)
Effect of Construction 1041 (1)
Die-to-Carrier Gap 1041 (1)
Thermal Performance 1042 (2)
Wafer Thinning 1042 (1)
Enhanced thermal conductivity 1042 (1)
Impedance match 1042 (1)
Cost implications 1042 (1)
Flip Chip vs. Wirebond 1042 (1)
Wirebond dice 1042 (1)
Flip-chip dice 1042 (1)
Examples 1043 (1)
Development For High-Frequency 1044 (1)
Consumer Products 1044 (1)
Products/Concepts Using Flip-Chip Dice 1044 (1)
Example applications 1044 (1)
Theoretical Evaluations and University 1044 (1)
Activities
Summary/Conclusions 1045 (1)
Future 1045 (4)
Acknowledgments 1046 (1)
References 1046 (3)
Thermal Performance 1049 (59)
Overall Considerations and Requirements 1049 (3)
Material Temperature Limits 1049 (1)
Electrical Performance 1050 (1)
Die/Package Reliability 1050 (1)
Main cycles 1050 (1)
Green cycles 1050 (1)
Mini cycles 1050 (1)
Ambient-related cycles 1050 (1)
Approach overview 1051 (1)
Physical Space Requirements 1052 (1)
Fundamental Concepts 1052 (9)
Heat Transfer Modes 1052 (1)
Overview---Conduction, Convection,
Radiation
Conduction 1052 (1)
Convection 1053 (1)
Radiation 1054 (1)
Language of Electronic Package Thermal 1055 (2)
Management
Dimensionless analysis of convective heat 1057 (2)
transfer
Modeling Approaches and Simplification 1059 (2)
2-D Model 1061 (1)
1-D Model 1061 (1)
Statistical Prediction of Field 1061 (1)
Performance
Measurements and Techniques 1061 (6)
Die Temperature Measurement 1062 (1)
Functional dice 1062 (1)
Thermal test dice 1063 (1)
Die temperature sensors 1064 (1)
Thermal-Resistance Parameter Measurement 1065 (1)
Package internal thermal 1066 (1)
resistance---θJC, θJB
Package external thermal 1067 (1)
resistance---θCA, θBA
Package Level Thermal Design 1067 (18)
Die-Level Packages 1067 (1)
Flip-Chip vs. Wire-Bond Dice 1068 (1)
Flip-Chip dice 1068 (1)
Wire-Bond dice 1068 (1)
Heat flow paths 1068 (1)
External resistance 1069 (2)
Effect of low I/O counts 1071 (1)
Plastic Ball Grid Array (PBGA) 1071 (1)
Heat flow paths 1071 (1)
Card effects 1071 (1)
Tape Ball Grid Array (TBGA) 1072 (1)
Thermal paths 1072 (1)
Effect of card construction 1073 (1)
Effect of die power dissipation 1074 (1)
Gradients 1074 (1)
CBGA/CCGA/CLGA 1075 (1)
I/O configurations 1075 (1)
Encapsulation options 1075 (1)
Internal/External thermal resistance 1076 (1)
Thermal resistance statistical variation 1077 (1)
Capped/Capless 1077 (1)
Effect of I/Os and underfill 1077 (1)
External resistance 1078 (2)
Effect of heat sinks 1080 (2)
Multi-Chip Modules 1082 (1)
High-power MCM cooling 1082 (2)
Low-power MCM cooling 1084 (1)
Interfacing to External Cooling 1084 (1)
Comparison to Non-Area Array Packaging 1085 (1)
Heat Sinks 1085 (12)
General Considerations 1085 (1)
Types/Configurations 1086 (1)
Flow-through or serially-cooled heat sinks 1086 (2)
Impingement heat sinks 1088 (1)
Fan sinks 1089 (1)
Natural Convection from Heat Sinks 1089 (1)
Design 1089 (1)
Spacing 1089 (1)
Radiation 1090 (1)
Methods of Attachment 1090 (1)
Mechanical 1090 (1)
Epoxy 1090 (1)
Thermal tapes (adhesive) 1090 (1)
Thermal Interface Materials 1091 (1)
Oils/Greases 1091 (1)
Conformable materials 1091 (1)
Phase-Change materials 1092 (1)
Calculating Thermal Performance 1093 (1)
Spreading resistance 1093 (1)
Fin efficiency 1093 (1)
Convection resistance 1094 (1)
Heat sink performance/optimization 1095 (2)
Air-Cooled Systems 1097 (6)
Fouling 1097 (1)
Heat Flow to/from Cards 1097 (1)
Natural/forced convection 1098 (1)
Effect of mounted components 1098 (1)
Conduction/radiation to surroundings 1099 (1)
Card ground planes/thermal vias 1100 (1)
Airflow Control 1100 (1)
``Spray'' flow 1100 (1)
Ducted flow 1101 (1)
Upstream air-heating 1102 (1)
Calculating local convection coefficients 1102 (1)
Future Thermal Enhancements 1103 (5)
Acknowledgments 1105 (1)
References 1105 (3)
Metallurgical Factors 1108 (37)
Introduction 1108 (2)
Manufacturing Issues 1108 (1)
Reliability Issues 1109 (1)
Effect of Phase Transformations on Area 1110 (2)
Array Interconnects
Equilibrium Pb-Sn System 1110 (1)
(Liquid + Solid) Phase Fields 1111 (1)
Hierarchical Soldering Requirements 1111 (1)
Coefficient of Thermal Expansion 1112 (1)
Metallurgical Systems and Processes 1112 (2)
Damaged Structure 1112 (1)
Processes for Structural Change 1112 (1)
Recovery 1113 (1)
Recrystallization 1113 (1)
Grain growth 1113 (1)
Effect of Multiple Phases 1114 (1)
Metallurgical Reactions and Intermetallic 1114 (6)
Compound Formation
Introduction 1114 (1)
Pad-Metallization Dissolution Kinetics 1115 (1)
Pad Metallization: Au 1115 (1)
Characteristics 1115 (1)
Dissolution in Sn and In-based solders 1116 (1)
Intermetallics formed and effects 1116 (1)
Pad Metallizations: Ag, Pd 1116 (1)
Characteristics 1116 (1)
Dissolution in Sn-based solders 1116 (1)
Intermetallics formed and effects 1116 (1)
Pad Metallizations: Cu, Ni, Pt 1116 (1)
Characteristics 1116 (1)
Dissolution in Sn or In-based solders 1117 (1)
Intermetallics formed and effects 1117 (1)
Morphology 1117 (1)
Growth Kinetics 1118 (1)
Determining coefficients 1118 (1)
Linear growth kinetics, n = 1 1119 (1)
Parabolic growth kinetics, n = 1/2 1119 (1)
Intermetallics at Pad Metallization 1119 (1)
Summary
Solder Alloy Systems 1120 (9)
Major Constituents 1120 (1)
Tin 1120 (1)
Lead 1120 (1)
Indium 1120 (1)
Pb-Sn Solder Alloys 1120 (1)
High Pb-content Pb-Sn solders 1121 (1)
Near-eutectic Sn-Pb solders 1122 (2)
Other Solder Alloys 1124 (1)
Sn-36Pb-2Ag 1125 (1)
50Pb-50In 1125 (1)
40Sn-40In-20Pb 1126 (1)
Pb-free solders 1126 (3)
Solder Wetting Behavior 1129 (1)
Wetting Determination and Optimization 1129 (1)
Wetting to Pad Metallizations 1130 (1)
Spalling of Intermetallics 1130 (2)
Die Attachment with Eutectic Sn-Pb 1131 (1)
Intermetallic Ripening 1131 (1)
Role of Microstructure on Properties and 1132 (4)
Joint Integrity
High Homologous Temperatures 1132 (1)
Intermetallics 1133 (1)
Interfacial layers 1133 (1)
Effect of Thermal Aging 1134 (1)
High-Pb content Pb-Sn solders 1134 (1)
Near-eutectic Sn-Pb solders 1135 (1)
Other solder alloys 1135 (1)
Solder Joint Mechanical Behavior 1136 (5)
Creep Behavior 1136 (1)
Description/importance 1136 (1)
Mechanism 1136 (1)
Damage/physical changes 1136 (1)
Creep rate 1136 (2)
Thermomechanical Fatigue 1138 (1)
Strain generation 1138 (1)
Fatigue of near-eutectic Sn-Pb solder 1138 (1)
joints
Fatigue of modified near-eutectic Sn-Pb 1139 (1)
joints
Fatigue of Pb-rich Pb-Sn solders 1139 (1)
Fatigue of Sn-40In-20Pb solder 1140 (1)
Fatigue of eutectic Sn-Ag based solders 1141 (1)
Dual Solder Joints 1141 (1)
Summary 1141 (4)
References 1142 (3)
Contributing Authors 1145 (18)
Index 1163