A Computer-Aided Design and Synthesis Environment for Analog Integrated Circuits (Kluwer International Series in Engineering and Computer Science Vol.672)

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A Computer-Aided Design and Synthesis Environment for Analog Integrated Circuits (Kluwer International Series in Engineering and Computer Science Vol.672)

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  • 製本 Hardcover:ハードカバー版/ページ数 236 p.
  • 言語 ENG
  • 商品コード 9780792376972
  • DDC分類 621.3815

Table of Contents

Abstract                                           i
List of Abbreviations iii
List of Symbols v
Contents ix
List of Figures xiii
List of Tables xvii
Introduction 1 (12)
Goals of this Work 9 (2)
Outline of this Work 11 (2)
I Automatic Synthesis of Analog Circuits 13 (100)
The AMGIE Analog Synthesis System 15 (24)
Introduction 15 (1)
Definitions 15 (4)
Overview of Analog Synthesis Research 19 (7)
Early Work 20 (1)
Second Generation 21 (2)
Most Recent Work 23 (2)
Conclusions 25 (1)
The AMGIE Synthesis System 26 (12)
Functionality of the Analog Synthesis 26 (8)
Environment
Software Architecture of the AMGIE System 34 (4)
Summary 38 (1)
Detailed Description of the AMGIE Analog 39 (34)
Synthesis System
Specifications and Hierarchy 39 (3)
Topology Selection Tool 42 (3)
Boundary Checking Filter 42 (2)
Interval Analysis Filter 44 (1)
Rule-based Ranking Filter 45 (1)
Sizing and Optimization Tool 45 (16)
Sizing Model Generation 47 (8)
Circuit Optimization Setup 55 (2)
Practical Example 57 (4)
Layout Generation Tool 61 (4)
Practical Example 64 (1)
Verification Tool 65 (5)
Nominal Performance Verification 66 (3)
Verification with Mismatch and Technology 69 (1)
Spread
Verification over Temperature and 70 (1)
Power-supply Operating Ranges
Redesign Wizard 70 (1)
Example Scenarios 70 (1)
Summary 71 (2)
AMGIE Experimental Results 73 (40)
Comparison of Analog Sizing Synthesis: 73 (6)
Equation-based vs. Simulation-based
Design Specifications 74 (1)
Manual Sizing 74 (1)
Simulation-based Sizing 75 (1)
Equation-based Sizing 76 (1)
Comparison & Conclusions 77 (2)
Student Exercise: High-speed Operational 79 (11)
Transconductance Amplifier
Setup 79 (1)
Session 79 (7)
Analysis of Results 86 (3)
Conclusions 89 (1)
Charge-Sensitive Amplifier - Pulse-Shaping 90 (18)
Amplifier
CSA-PSA Specifications 91 (1)
CSA-PSA Architecture 92 (9)
Topology Selection 101 (1)
Sizing Synthesis: OPTIMAN 102 (1)
Layout Generation 102 (4)
Verification 106 (1)
Measurement Results 106 (1)
Conclusions 107 (1)
Summary 108 (5)
Conclusions 109 (4)
II Systematic Design of Analog Circuits 113 (80)
Introduction 115 (2)
Mondriaan: a Layout Synthesis Methodology for 117 (28)
Array-type Analog Analog Blocks
Requirements of the New Layout Generation 119 (1)
Methodology
Description of the Layout Model 120 (3)
Description of the Layout Generation 123 (7)
Methodology
Floorplanning 124 (1)
Symbolic Routing 125 (1)
Technology Mapping 126 (1)
Bus and Tree Generators 127 (3)
Illustrative Example 130 (7)
Current Source Array 130 (3)
Switch/Latch Array 133 (2)
Assembly 135 (1)
Conclusions 136 (1)
Experimental Results 137 (6)
Folding/Interpolating A/D-converter 137 (3)
Modules
Current-Steering D/A-converter Modules 140 (3)
Conclusions 143 (2)
Systematic Design of Current-Steering 145 (44)
D/A-converters
Functionblock Design Flow 146 (2)
Current-Steering D/A-converter Architecture 148 (4)
Operating Principle and Specifications 148 (1)
Proposed Architecture and its Design 149 (3)
Parameters
Behavioral Modeling for the Specification 152 (2)
Phase
Dynamic Behavior 152 (2)
Static Behavior 154 (1)
Synthesis Flow of the D/A-converter 154 (2)
Sizing Synthesis 156 (7)
Architectural-level Synthesis 156 (3)
Circuit-level Synthesis 159 (2)
Full Decoder Synthesis 161 (2)
Clock Driver Synthesis 163 (1)
Layout Generation 163 (15)
Floorplanning 163 (1)
Current Source Array Layout Generation 164 (12)
Swatch Array Layout Generation 176 (1)
Full Decoder Standard Cell Place and Route 177 (1)
Layout Assembly 177 (1)
Extraction of a Behavioral Model for 178 (3)
Verification
Static Behavior: INL 178 (1)
Dynamic Behavior: Glitch Energy 179 (2)
Experimental Results 181 (5)
Measurement Setup 181 (1)
Measurement Results 182 (2)
Breakdown of Design Time 184 (2)
Conclusions 186 (3)
Conclusions 189 (4)
Bibliography 193 (12)
Index 205